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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk03f5c552004-10-10 21:21:55 +00002/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06003 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00004 */
5
6/*
7 * mpc8555cds board configuration file
8 *
9 * Please refer to doc/README.mpc85xxcds for more info.
10 *
11 */
wdenk03f5c552004-10-10 21:21:55 +000012#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/* High Level Configuration Options */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050016#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000017
Gabor Juhos842033e2013-05-30 07:06:12 +000018#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050019#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
wdenk03f5c552004-10-10 21:21:55 +000020#define CONFIG_ENV_OVERWRITE
wdenk03f5c552004-10-10 21:21:55 +000021
Jon Loeliger25eedb22008-03-19 15:02:07 -050022#define CONFIG_FSL_VIA
Timur Tabie8d18542008-07-18 16:52:23 +020023
wdenk03f5c552004-10-10 21:21:55 +000024#ifndef __ASSEMBLY__
25extern unsigned long get_clock_freq(void);
26#endif
27#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
28
29/*
30 * These can be toggled for performance analysis, otherwise use default.
31 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020032#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000033#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000034
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
36#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000037
Timur Tabie46fedf2011-08-04 18:03:41 -050038#define CONFIG_SYS_CCSRBAR 0xe0000000
39#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk03f5c552004-10-10 21:21:55 +000040
Jon Loeliger2b40edb2008-03-18 11:12:42 -050041/* DDR Setup */
Jon Loeliger2b40edb2008-03-18 11:12:42 -050042#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
43#define CONFIG_DDR_SPD
44#undef CONFIG_FSL_DDR_INTERACTIVE
45
46#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
47
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
49#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000050
Jon Loeliger2b40edb2008-03-18 11:12:42 -050051#define CONFIG_DIMM_SLOTS_PER_CTLR 1
52#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk03f5c552004-10-10 21:21:55 +000053
Jon Loeliger2b40edb2008-03-18 11:12:42 -050054/* I2C addresses of SPD EEPROMs */
55#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
56
57/* Make sure required options are set */
wdenk03f5c552004-10-10 21:21:55 +000058#ifndef CONFIG_SPD_EEPROM
59#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
60#endif
61
Jon Loeliger7202d432005-07-25 11:13:26 -050062#undef CONFIG_CLOCKS_IN_MHZ
63
wdenk03f5c552004-10-10 21:21:55 +000064/*
Jon Loeliger7202d432005-07-25 11:13:26 -050065 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +000066 */
Jon Loeliger7202d432005-07-25 11:13:26 -050067
68/*
69 * FLASH on the Local Bus
70 * Two banks, 8M each, using the CFI driver.
71 * Boot from BR0/OR0 bank at 0xff00_0000
72 * Alternate BR1/OR1 bank at 0xff80_0000
73 *
74 * BR0, BR1:
75 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
76 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
77 * Port Size = 16 bits = BRx[19:20] = 10
78 * Use GPCM = BRx[24:26] = 000
79 * Valid = BRx[31] = 1
80 *
81 * 0 4 8 12 16 20 24 28
82 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
83 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
84 *
85 * OR0, OR1:
86 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
87 * Reserved ORx[17:18] = 11, confusion here?
88 * CSNT = ORx[20] = 1
89 * ACS = half cycle delay = ORx[21:22] = 11
90 * SCY = 6 = ORx[24:27] = 0110
91 * TRLX = use relaxed timing = ORx[29] = 1
92 * EAD = use external address latch delay = OR[31] = 1
93 *
94 * 0 4 8 12 16 20 24 28
95 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
96 */
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_BR0_PRELIM 0xff801001
101#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_OR0_PRELIM 0xff806e65
104#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
107#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
108#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
109#undef CONFIG_SYS_FLASH_CHECKSUM
110#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
111#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000112
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200113#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000114
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200115#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_FLASH_CFI
117#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000118
wdenk03f5c552004-10-10 21:21:55 +0000119/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500120 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000121 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
123#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000124
125/*
126 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000128 *
129 * For BR2, need:
130 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
131 * port-size = 32-bits = BR2[19:20] = 11
132 * no parity checking = BR2[21:22] = 00
133 * SDRAM for MSEL = BR2[24:26] = 011
134 * Valid = BR[31] = 1
135 *
136 * 0 4 8 12 16 20 24 28
137 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
138 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000140 * FIXME: the top 17 bits of BR2.
141 */
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000144
145/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000147 *
148 * For OR2, need:
149 * 64MB mask for AM, OR2[0:7] = 1111 1100
150 * XAM, OR2[17:18] = 11
151 * 9 columns OR2[19-21] = 010
152 * 13 rows OR2[23-25] = 100
153 * EAD set for extra time OR[31] = 1
154 *
155 * 0 4 8 12 16 20 24 28
156 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
157 */
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
162#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
163#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
164#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000165
166/*
wdenk03f5c552004-10-10 21:21:55 +0000167 * Common settings for all Local Bus SDRAM commands.
168 * At run time, either BSMA1516 (for CPU 1.1)
169 * or BSMA1617 (for CPU 1.0) (old)
170 * is OR'ed in too.
171 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500172#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
173 | LSDMR_PRETOACT7 \
174 | LSDMR_ACTTORW7 \
175 | LSDMR_BL8 \
176 | LSDMR_WRC4 \
177 | LSDMR_CL3 \
178 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000179 )
180
181/*
182 * The CADMUS registers are connected to CS3 on CDS.
183 * The new memory map places CADMUS at 0xf8000000.
184 *
185 * For BR3, need:
186 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
187 * port-size = 8-bits = BR[19:20] = 01
188 * no parity checking = BR[21:22] = 00
189 * GPMC for MSEL = BR[24:26] = 000
190 * Valid = BR[31] = 1
191 *
192 * 0 4 8 12 16 20 24 28
193 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
194 *
195 * For OR3, need:
196 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
197 * disable buffer ctrl OR[19] = 0
198 * CSNT OR[20] = 1
199 * ACS OR[21:22] = 11
200 * XACS OR[23] = 1
201 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
202 * SETA OR[28] = 0
203 * TRLX OR[29] = 1
204 * EHTR OR[30] = 1
205 * EAD extra time OR[31] = 1
206 *
207 * 0 4 8 12 16 20 24 28
208 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
209 */
210
Jon Loeliger25eedb22008-03-19 15:02:07 -0500211#define CONFIG_FSL_CADMUS
212
wdenk03f5c552004-10-10 21:21:55 +0000213#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_BR3_PRELIM 0xf8000801
215#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_RAM_LOCK 1
218#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200219#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000220
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
225#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000226
227/* Serial Port */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NS16550_SERIAL
229#define CONFIG_SYS_NS16550_REG_SIZE 1
230#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
236#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000237
Jon Loeliger20476722006-10-20 15:50:15 -0500238/*
239 * I2C
240 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200241#define CONFIG_SYS_I2C
242#define CONFIG_SYS_I2C_FSL
243#define CONFIG_SYS_FSL_I2C_SPEED 400000
244#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
245#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
246#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk03f5c552004-10-10 21:21:55 +0000247
Timur Tabie8d18542008-07-18 16:52:23 +0200248/* EEPROM */
249#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_I2C_EEPROM_CCID
251#define CONFIG_SYS_ID_EEPROM
252#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
253#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200254
wdenk03f5c552004-10-10 21:21:55 +0000255/*
256 * General PCI
257 * Addresses are mapped 1-1.
258 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600259#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600260#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600261#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600263#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600264#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
266#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000267
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600268#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600269#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600270#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600272#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600273#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
275#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000276
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700277#ifdef CONFIG_LEGACY
278#define BRIDGE_ID 17
279#define VIA_ID 2
280#else
281#define BRIDGE_ID 28
282#define VIA_ID 4
283#endif
wdenk03f5c552004-10-10 21:21:55 +0000284
285#if defined(CONFIG_PCI)
286
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500287#define CONFIG_MPC85XX_PCI2
wdenk03f5c552004-10-10 21:21:55 +0000288
289#undef CONFIG_EEPRO100
290#undef CONFIG_TULIP
291
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500292#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000294
295#endif /* CONFIG_PCI */
296
wdenk03f5c552004-10-10 21:21:55 +0000297#if defined(CONFIG_TSEC_ENET)
298
Kim Phillips255a35772007-05-16 16:52:19 -0500299#define CONFIG_TSEC1 1
300#define CONFIG_TSEC1_NAME "TSEC0"
301#define CONFIG_TSEC2 1
302#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000303#define TSEC1_PHY_ADDR 0
304#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000305#define TSEC1_PHYIDX 0
306#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500307#define TSEC1_FLAGS TSEC_GIGABIT
308#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500309
310/* Options are: TSEC[0-1] */
311#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000312
313#endif /* CONFIG_TSEC_ENET */
314
wdenk03f5c552004-10-10 21:21:55 +0000315/*
316 * Environment
317 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200319#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
320#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000321
322#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000324
Jon Loeliger2835e512007-06-13 13:22:08 -0500325/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500326 * BOOTP options
327 */
328#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeliger659e2f62007-07-10 09:10:49 -0500329
wdenk03f5c552004-10-10 21:21:55 +0000330#undef CONFIG_WATCHDOG /* watchdog disabled */
331
332/*
333 * Miscellaneous configurable options
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
wdenk03f5c552004-10-10 21:21:55 +0000336
337/*
338 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500339 * have to be in the first 64 MB of memory, since this is
wdenk03f5c552004-10-10 21:21:55 +0000340 * the maximum mapped by the Linux kernel during initialization.
341 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500342#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
343#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk03f5c552004-10-10 21:21:55 +0000344
Jon Loeliger2835e512007-06-13 13:22:08 -0500345#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000346#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk03f5c552004-10-10 21:21:55 +0000347#endif
348
wdenk03f5c552004-10-10 21:21:55 +0000349/*
350 * Environment Configuration
351 */
wdenk03f5c552004-10-10 21:21:55 +0000352#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500353#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000354#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000355#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000356#endif
357
358#define CONFIG_IPADDR 192.168.1.253
359
Mario Six5bc05432018-03-28 14:38:20 +0200360#define CONFIG_HOSTNAME "unknown"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000361#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000362#define CONFIG_BOOTFILE "your.uImage"
wdenk03f5c552004-10-10 21:21:55 +0000363
364#define CONFIG_SERVERIP 192.168.1.1
365#define CONFIG_GATEWAYIP 192.168.1.1
366#define CONFIG_NETMASK 255.255.255.0
367
368#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
369
wdenk03f5c552004-10-10 21:21:55 +0000370#define CONFIG_EXTRA_ENV_SETTINGS \
371 "netdev=eth0\0" \
372 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500373 "ramdiskaddr=600000\0" \
374 "ramdiskfile=your.ramdisk.u-boot\0" \
375 "fdtaddr=400000\0" \
376 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000377
378#define CONFIG_NFSBOOTCOMMAND \
379 "setenv bootargs root=/dev/nfs rw " \
380 "nfsroot=$serverip:$rootpath " \
381 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
382 "console=$consoledev,$baudrate $othbootargs;" \
383 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500384 "tftp $fdtaddr $fdtfile;" \
385 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000386
387#define CONFIG_RAMBOOTCOMMAND \
388 "setenv bootargs root=/dev/ram rw " \
389 "console=$consoledev,$baudrate $othbootargs;" \
390 "tftp $ramdiskaddr $ramdiskfile;" \
391 "tftp $loadaddr $bootfile;" \
392 "bootm $loadaddr $ramdiskaddr"
393
394#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
395
wdenk03f5c552004-10-10 21:21:55 +0000396#endif /* __CONFIG_H */