| Andre Schwarz | a1293e5 | 2008-06-10 09:14:05 +0200 | [diff] [blame] | 1 | #ifndef __MVBC_H__ |
| 2 | #define __MVBC_H__ |
| 3 | |
| 4 | #define MV_GPIO |
| 5 | |
| 6 | #define FPGA_CONFIG 0x80000000 |
| 7 | #define FPGA_CCLK 0x40000000 |
| 8 | #define FPGA_DIN 0x20000000 |
| 9 | #define FPGA_STATUS 0x10000000 |
| 10 | #define FPGA_CONF_DONE 0x08000000 |
| Andre Schwarz | a1293e5 | 2008-06-10 09:14:05 +0200 | [diff] [blame] | 11 | |
| 12 | #define WD_WDI 0x00400000 |
| 13 | #define WD_TS 0x00200000 |
| 14 | #define MAN_RST 0x00100000 |
| 15 | |
| 16 | #define MV_GPIO_DAT (WD_TS) |
| André Schwarz | 28887d8 | 2009-08-27 14:48:35 +0200 | [diff] [blame] | 17 | #define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) |
| Andre Schwarz | a1293e5 | 2008-06-10 09:14:05 +0200 | [diff] [blame] | 18 | #define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) |
| 19 | |
| 20 | #endif |