blob: 9cfa0873452e120346421ea121bf9ffc10a7981a [file] [log] [blame]
wdenkc12b5a32002-08-20 16:13:03 +00001/*
2 * (C) Copyright 2001
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2001
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenkc12b5a32002-08-20 16:13:03 +00009 */
10
11/*
12 * board/config.h - configuration options, board specific
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
22
23#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
24#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0x40000000
27
wdenkc12b5a32002-08-20 16:13:03 +000028/*#define CONFIG_VIDEO 1 */
29
30#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
31#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
32#undef CONFIG_8xx_CONS_SMC2
33#undef CONFIG_8xx_CONS_NONE
34#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */
35#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
Detlev Zundele5084af2008-02-22 17:21:32 +010036#define CONFIG_BOOTARGS "ramdisk_size=8000 "\
wdenkc12b5a32002-08-20 16:13:03 +000037 "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
38 "nfsaddrs=10.77.77.20:10.77.77.250"
39#define CONFIG_BOOTCOMMAND "bootm 400e0000"
40
41#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkc12b5a32002-08-20 16:13:03 +000043#undef CONFIG_WATCHDOG /* watchdog disabled, for now */
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020044#define CONFIG_SOURCE
wdenkc12b5a32002-08-20 16:13:03 +000045
Jon Loeliger7be044e2007-07-09 21:24:19 -050046/*
47 * BOOTP options
48 */
49#define CONFIG_BOOTP_SUBNETMASK
50#define CONFIG_BOOTP_GATEWAY
51#define CONFIG_BOOTP_HOSTNAME
52#define CONFIG_BOOTP_BOOTPATH
53#define CONFIG_BOOTP_BOOTFILESIZE
54
Jon Loeligere18a1062007-07-08 14:21:43 -050055
56/*
57 * Command line configuration.
58 */
59#include <config_cmd_default.h>
60
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020061#define CONFIG_CMD_SOURCE
Jon Loeligere18a1062007-07-08 14:21:43 -050062
63
wdenkc12b5a32002-08-20 16:13:03 +000064/* call various generic functions */
65#define CONFIG_MISC_INIT_R
66
wdenkc12b5a32002-08-20 16:13:03 +000067/*
68 * Miscellaneous configurable options
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_LONGHELP /* undef to save memory */
71#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere18a1062007-07-08 14:21:43 -050072#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc12b5a32002-08-20 16:13:03 +000074#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc12b5a32002-08-20 16:13:03 +000076#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
78#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
79#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc12b5a32002-08-20 16:13:03 +000080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
82#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc12b5a32002-08-20 16:13:03 +000083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkc12b5a32002-08-20 16:13:03 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc12b5a32002-08-20 16:13:03 +000087
wdenkc12b5a32002-08-20 16:13:03 +000088/*
89 * Low Level Configuration Settings
90 * (address mappings, register initial values, etc.)
91 * You should know what you are doing if you make changes here.
92 */
93/*-----------------------------------------------------------------------
94 * Internal Memory Mapped Register
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_IMMR 0xFFF00000
wdenkc12b5a32002-08-20 16:13:03 +000097
98/*-----------------------------------------------------------------------
99 * Definitions for initial stack pointer and data area (in DPRAM)
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200102#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200103#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc12b5a32002-08-20 16:13:03 +0000105
106/*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc12b5a32002-08-20 16:13:03 +0000110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_SDRAM_BASE 0x00000000
112#define CONFIG_SYS_FLASH_BASE 0x40000000
113#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
114#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
115#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc12b5a32002-08-20 16:13:03 +0000116
117/*
118 * For booting Linux, the board info and command line data
119 * have to be in the first 8 MB of memory, since this is
120 * the maximum mapped by the Linux kernel during initialization.
121 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc12b5a32002-08-20 16:13:03 +0000123
124/*-----------------------------------------------------------------------
125 * FLASH organization
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
128#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkc12b5a32002-08-20 16:13:03 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
131#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc12b5a32002-08-20 16:13:03 +0000132
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200133#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc12b5a32002-08-20 16:13:03 +0000134#define xEMBED
135#ifdef EMBED
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200136#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE
wdenkc12b5a32002-08-20 16:13:03 +0000138#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200139#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */
140#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
wdenkc12b5a32002-08-20 16:13:03 +0000141#endif
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */
144#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */
145#define CONFIG_SYS_FLASH_SN_BYTES 8
wdenkc12b5a32002-08-20 16:13:03 +0000146
147/*-----------------------------------------------------------------------
148 * Cache Configuration
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere18a1062007-07-08 14:21:43 -0500151#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkc12b5a32002-08-20 16:13:03 +0000153#endif
154
155/*-----------------------------------------------------------------------
156 * SYPCR - System Protection Control 11-9
157 * SYPCR can only be written once after reset!
158 *-----------------------------------------------------------------------
159 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
160 */
161#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkc12b5a32002-08-20 16:13:03 +0000163 SYPCR_SWE | SYPCR_SWP)
164#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkc12b5a32002-08-20 16:13:03 +0000166#endif
167
168/*-----------------------------------------------------------------------
169 * SIUMCR - SIU Module Configuration 12-30
170 *-----------------------------------------------------------------------
171 * PCMCIA config., multi-function pin tri-state
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00)
wdenkc12b5a32002-08-20 16:13:03 +0000174
175/*-----------------------------------------------------------------------
176 * TBSCR - Time Base Status and Control 12-16
177 *-----------------------------------------------------------------------
178 * Clear Reference Interrupt Status, Timebase freezing enabled
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkc12b5a32002-08-20 16:13:03 +0000181
182/*-----------------------------------------------------------------------
183 * RTCSC - Real-Time Clock Status and Control Register 12-18
184 *-----------------------------------------------------------------------
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkc12b5a32002-08-20 16:13:03 +0000187
188/*-----------------------------------------------------------------------
189 * PISCR - Periodic Interrupt Status and Control 12-23
190 *-----------------------------------------------------------------------
191 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkc12b5a32002-08-20 16:13:03 +0000194
195/*-----------------------------------------------------------------------
196 * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7
197 *-----------------------------------------------------------------------
198 * Reset PLL lock status sticky bit, timer expired status bit and timer
199 * interrupt status bit
200 */
201#define MPC8XX_SPEED 66666666L
202#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */
203#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
205#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkc12b5a32002-08-20 16:13:03 +0000206
207/*-----------------------------------------------------------------------
208 * SCCR - System Clock and reset Control Register 5-3
209 *-----------------------------------------------------------------------
210 * Set clock output, timebase and RTC source and divider,
211 * power management and some other internal clocks
212 */
213#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenkc12b5a32002-08-20 16:13:03 +0000215 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
216 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
217 SCCR_DFALCD00)
218
219/*-----------------------------------------------------------------------
220 *
221 *-----------------------------------------------------------------------
222 *
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_DER 0
wdenkc12b5a32002-08-20 16:13:03 +0000225
226/*
227 * Init Memory Controller:
228 *
229 * BR0 and OR0 (FLASH)
230 */
231
232#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
233
234/* used to re-map FLASH both when starting from SRAM or FLASH:
235 * restrict access enough to keep SRAM working (if any)
236 * but not too much to meddle with FLASH accesses
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
239#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkc12b5a32002-08-20 16:13:03 +0000240
241/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
wdenkc12b5a32002-08-20 16:13:03 +0000243 OR_SCY_8_CLK )
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
246#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
247#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenkc12b5a32002-08-20 16:13:03 +0000248
249/*
250 * BR1/2 and OR1/2 (SDRAM)
251 */
252#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
253#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
254#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
255
256/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM)
wdenkc12b5a32002-08-20 16:13:03 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
260#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
261#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM
262#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkc12b5a32002-08-20 16:13:03 +0000263
264/* IO and memory mapped stuff */
265#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */
266#define NX823_IO_BASE 0xFF000000 /* start of IO */
267#define GPOUT_OFFSET (3<<16)
268#define QUART_OFFSET (4<<16)
269#define VIDAC_OFFSET (5<<16)
270#define CPLD_OFFSET (6<<16)
271#define SED1386_OFFSET (7<<16)
272
273/*
274 * BR3 and OR3 (general purpose output latches)
275 */
276#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET)
277#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING)
279#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V)
wdenkc12b5a32002-08-20 16:13:03 +0000280
281/*
282 * BR4 and OR4 (QUART)
283 */
284#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET)
285#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
287#define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V)
wdenkc12b5a32002-08-20 16:13:03 +0000288
289/*
290 * BR5 and OR5 (Video DAC)
291 */
292#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET)
293#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
295#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V)
wdenkc12b5a32002-08-20 16:13:03 +0000296
297/*
298 * BR6 and OR6 (CPLD)
299 * FIXME timing not verified for CPLD
300 */
301#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET)
302#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
304#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V )
wdenkc12b5a32002-08-20 16:13:03 +0000305
306/*
307 * BR7 and OR7 (SED1386)
308 * FIXME timing not verified for SED controller
309 */
310#define SED1386_BASE 0xF7000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA)
312#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V )
wdenkc12b5a32002-08-20 16:13:03 +0000313
314/*
315 * Memory Periodic Timer Prescaler
316 */
317
318/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenkc12b5a32002-08-20 16:13:03 +0000320
321/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
323#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkc12b5a32002-08-20 16:13:03 +0000324
325/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
327#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkc12b5a32002-08-20 16:13:03 +0000328
329/*
330 * MAMR settings for SDRAM
331 */
332
333/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc12b5a32002-08-20 16:13:03 +0000335 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
336 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
337/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc12b5a32002-08-20 16:13:03 +0000339 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
340 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
341
wdenkc12b5a32002-08-20 16:13:03 +0000342#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
343#define CONFIG_ETHADDR 00:10:20:30:40:50
344#define CONFIG_IPADDR 10.77.77.20
345#define CONFIG_SERVERIP 10.77.77.250
346
347#endif /* __CONFIG_H */