wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000, 2001, 2002 |
| 3 | * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. |
| 4 | * |
| 5 | * Configuration for the Cogent CSB226 board. For details see |
| 6 | * http://www.cogcomp.com/csb_csb226.htm |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * include/configs/csb226.h - configuration options, board specific |
| 29 | */ |
| 30 | |
| 31 | #ifndef __CONFIG_H |
| 32 | #define __CONFIG_H |
| 33 | |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame^] | 34 | #define DEBUG 1 |
| 35 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 36 | /* |
| 37 | * If we are developing, we might want to start U-Boot from ram |
| 38 | * so we MUST NOT initialize critical regs like mem-timing ... |
| 39 | */ |
| 40 | #define CONFIG_INIT_CRITICAL /* undef for developing */ |
| 41 | |
| 42 | /* |
| 43 | * High Level Configuration Options |
| 44 | * (easy to change) |
| 45 | */ |
| 46 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ |
| 47 | #define CONFIG_CSB226 1 /* on a CSB226 board */ |
| 48 | |
| 49 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| 50 | /* for timer/console/ethernet */ |
| 51 | /* |
| 52 | * Hardware drivers |
| 53 | */ |
| 54 | |
| 55 | /* |
| 56 | * select serial console configuration |
| 57 | */ |
| 58 | #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ |
| 59 | |
| 60 | /* allow to overwrite serial and ethaddr */ |
| 61 | #define CONFIG_ENV_OVERWRITE |
| 62 | |
| 63 | #define CONFIG_BAUDRATE 19200 |
| 64 | |
| 65 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) |
| 66 | |
| 67 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 68 | #include <cmd_confdefs.h> |
| 69 | |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame^] | 70 | #define CONFIG_BOOTDELAY 3 |
| 71 | #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 72 | #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF |
| 73 | #define CONFIG_NETMASK 255.255.255.0 |
| 74 | #define CONFIG_IPADDR 192.168.1.56 |
| 75 | #define CONFIG_SERVERIP 192.168.1.2 |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame^] | 76 | #define CONFIG_BOOTCOMMAND "bootm 0x40000" |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 77 | |
| 78 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 79 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
| 80 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 81 | #endif |
| 82 | |
| 83 | /* |
| 84 | * Miscellaneous configurable options |
| 85 | */ |
| 86 | |
| 87 | /* |
| 88 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are |
| 89 | * used for the RAM copy of the uboot code |
| 90 | * |
| 91 | */ |
| 92 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
| 93 | |
| 94 | #define CFG_LONGHELP /* undef to save memory */ |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame^] | 95 | #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ |
| 96 | #define CFG_CBSIZE 128 /* Console I/O Buffer Size */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 97 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 98 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 99 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 100 | |
| 101 | #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ |
| 102 | #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
| 103 | |
| 104 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
| 105 | |
| 106 | #define CFG_LOAD_ADDR 0xa7fe0000 /* default load address */ |
| 107 | /* RS: where is this documented? */ |
| 108 | /* RS: is this where U-Boot is */ |
| 109 | /* RS: relocated to in RAM? */ |
| 110 | |
| 111 | #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
| 112 | /* RS: the oscillator is actually 3680130?? */ |
| 113 | #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ |
| 114 | /* 0101000001 */ |
| 115 | /* ^^^^^ Memory Speed 99.53 MHz */ |
| 116 | /* ^^ Run Mode Speed = 2x Mem Speed */ |
| 117 | /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ |
| 118 | |
| 119 | #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ |
| 120 | |
| 121 | /* valid baudrates */ |
| 122 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 123 | |
| 124 | /* |
| 125 | * Stack sizes |
| 126 | * |
| 127 | * The stack sizes are set up in start.S using the settings below |
| 128 | */ |
| 129 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
| 130 | #ifdef CONFIG_USE_IRQ |
| 131 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
| 132 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
| 133 | #endif |
| 134 | |
| 135 | /* |
| 136 | * Physical Memory Map |
| 137 | */ |
| 138 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| 139 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
| 140 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
| 141 | |
| 142 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| 143 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ |
| 144 | |
| 145 | #define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ |
| 146 | #define CFG_DRAM_SIZE 0x02000000 |
| 147 | |
| 148 | #define CFG_FLASH_BASE PHYS_FLASH_1 |
| 149 | |
| 150 | /* |
| 151 | * GPIO settings |
| 152 | */ |
| 153 | #define CFG_GPSR0_VAL 0xFFFFFFFF |
| 154 | #define CFG_GPSR1_VAL 0xFFFFFFFF |
| 155 | #define CFG_GPSR2_VAL 0xFFFFFFFF |
| 156 | #define CFG_GPCR0_VAL 0x08022080 |
| 157 | #define CFG_GPCR1_VAL 0x00000000 |
| 158 | #define CFG_GPCR2_VAL 0x00000000 |
| 159 | #define CFG_GPDR0_VAL 0xCD82A858 |
| 160 | #define CFG_GPDR1_VAL 0xFCFFAB80 |
| 161 | #define CFG_GPDR2_VAL 0x0001FFFF |
| 162 | #define CFG_GAFR0_L_VAL 0x80000000 |
| 163 | #define CFG_GAFR0_U_VAL 0xA5254010 |
| 164 | #define CFG_GAFR1_L_VAL 0x599A9550 |
| 165 | #define CFG_GAFR1_U_VAL 0xAAA5AAAA |
| 166 | #define CFG_GAFR2_L_VAL 0xAAAAAAAA |
| 167 | #define CFG_GAFR2_U_VAL 0x00000002 |
| 168 | |
| 169 | /* FIXME: set GPIO_RER/FER */ |
| 170 | |
| 171 | #define CFG_PSSR_VAL 0x20 |
| 172 | |
| 173 | /* |
| 174 | * Memory settings |
| 175 | */ |
| 176 | #define CFG_MSC0_VAL 0x2EF025D0 |
| 177 | #define CFG_MSC1_VAL 0x00003F64 |
| 178 | #define CFG_MSC2_VAL 0x00000000 |
| 179 | #define CFG_MDCNFG_VAL 0x09a909a9 |
| 180 | #define CFG_MDREFR_VAL 0x03ca0030 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 181 | #define CFG_MDMRS_VAL 0x00220022 |
| 182 | |
| 183 | /* |
| 184 | * PCMCIA and CF Interfaces |
| 185 | */ |
| 186 | #define CFG_MECR_VAL 0x00000000 |
| 187 | #define CFG_MCMEM0_VAL 0x00000000 |
| 188 | #define CFG_MCMEM1_VAL 0x00000000 |
| 189 | #define CFG_MCATT0_VAL 0x00000000 |
| 190 | #define CFG_MCATT1_VAL 0x00000000 |
| 191 | #define CFG_MCIO0_VAL 0x00000000 |
| 192 | #define CFG_MCIO1_VAL 0x00000000 |
| 193 | |
| 194 | /* |
| 195 | #define _LED 0x08000010 |
| 196 | #define LED_BLANK (0x08000040) |
| 197 | */ |
| 198 | |
| 199 | /* |
| 200 | * FLASH and environment organization |
| 201 | */ |
| 202 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 203 | #define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ |
| 204 | |
| 205 | /* timeout values are in ticks */ |
| 206 | #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ |
| 207 | #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ |
| 208 | |
| 209 | #define CFG_ENV_IS_IN_FLASH 1 |
| 210 | #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) |
| 211 | /* Addr of Environment Sector */ |
| 212 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
| 213 | |
| 214 | #endif /* __CONFIG_H */ |