blob: 2de4e980e465e09876aa8a2197bbe9e51df9e3ea [file] [log] [blame]
Kever Yang18f85082019-07-09 22:05:55 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <debug_uart.h>
8#include <dm.h>
Simon Glassdb41d652019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass691d7192020-05-10 11:40:02 -060010#include <init.h>
Kever Yang18f85082019-07-09 22:05:55 +080011#include <ram.h>
12#include <spl.h>
13#include <version.h>
14#include <asm/io.h>
15#include <asm/arch-rockchip/bootrom.h>
16
17#define TIMER_LOAD_COUNT_L 0x00
18#define TIMER_LOAD_COUNT_H 0x04
19#define TIMER_CONTROL_REG 0x10
20#define TIMER_EN 0x1
21#define TIMER_FMODE BIT(0)
22#define TIMER_RMODE BIT(1)
23
24__weak void rockchip_stimer_init(void)
25{
26 /* If Timer already enabled, don't re-init it */
27 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
28
29 if (reg & TIMER_EN)
30 return;
31
32#ifndef CONFIG_ARM64
33 asm volatile("mcr p15, 0, %0, c14, c0, 0"
34 : : "r"(COUNTER_FREQUENCY));
35#endif
36
37 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
38 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
39 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
40 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
41 TIMER_CONTROL_REG);
42}
43
Suniel Mahesh5a6d3d12020-02-03 19:20:05 +053044__weak int board_early_init_f(void)
45{
46 return 0;
47}
48
Kever Yang18f85082019-07-09 22:05:55 +080049void board_init_f(ulong dummy)
50{
51 struct udevice *dev;
52 int ret;
53
Suniel Mahesh5a6d3d12020-02-03 19:20:05 +053054 board_early_init_f();
55
Chris Webb58fcb032019-07-19 14:23:11 +010056#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
Kever Yang18f85082019-07-09 22:05:55 +080057 /*
58 * Debug UART can be used from here if required:
59 *
60 * debug_uart_init();
61 * printch('a');
62 * printhex8(0x1234);
63 * printascii("string");
64 */
65 debug_uart_init();
Chris Webb89e39172019-07-19 14:23:55 +010066#ifdef CONFIG_TPL_BANNER_PRINT
Kever Yang18f85082019-07-09 22:05:55 +080067 printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
68 U_BOOT_TIME ")\n");
69#endif
Chris Webb89e39172019-07-19 14:23:55 +010070#endif
Kever Yang18f85082019-07-09 22:05:55 +080071 ret = spl_early_init();
72 if (ret) {
73 debug("spl_early_init() failed: %d\n", ret);
74 hang();
75 }
76
77 /* Init secure timer */
78 rockchip_stimer_init();
79 /* Init ARM arch timer in arch/arm/cpu/ */
80 timer_init();
81
82 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
83 if (ret) {
84 printf("DRAM init failed: %d\n", ret);
85 return;
86 }
87}
88
Peng Fancda789a2019-08-07 06:40:53 +000089int board_return_to_bootrom(struct spl_image_info *spl_image,
90 struct spl_boot_device *bootdev)
Kever Yang18f85082019-07-09 22:05:55 +080091{
92 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
Peng Fancda789a2019-08-07 06:40:53 +000093
94 return 0;
Kever Yang18f85082019-07-09 22:05:55 +080095}
96
97u32 spl_boot_device(void)
98{
99 return BOOT_DEVICE_BOOTROM;
100}