Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 68f9c1e754bd3c68495d0952c29853035c59e60a / . / include / configs / XPEDITE5370.h
blob: 65e1afddc6930109f638184ebce13040e9c2bd12 [file] [log] [blame]
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]1/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * xpedite5370 board configuration file
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8572 1
37#define CONFIG_XPEDITE5370 1
38#define CONFIG_SYS_BOARD_NAME "XPedite5370"
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]39#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
40#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
41
42#define CONFIG_PCI 1 /* Enable PCI/PCIE */
43#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
44#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
45#define CONFIG_PCIE1 1 /* PCIE controler 1 */
46#define CONFIG_PCIE2 1 /* PCIE controler 2 */
47#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
48#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
49#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
50#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
51
52/*
53 * DDR config
54 */
55#define CONFIG_FSL_DDR2
56#undef CONFIG_FSL_DDR_INTERACTIVE
57#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
58#define CONFIG_DDR_SPD
59#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
60#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
61#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
62#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
63#define CONFIG_NUM_DDR_CONTROLLERS 2
64#define CONFIG_DIMM_SLOTS_PER_CTLR 1
65#define CONFIG_CHIP_SELECTS_PER_CTRL 1
66#define CONFIG_DDR_ECC
67#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
68#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
69#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
70#define CONFIG_VERY_BIG_RAM
71
72#ifndef __ASSEMBLY__
73extern unsigned long get_board_sys_clk(unsigned long dummy);
74extern unsigned long get_board_ddr_clk(unsigned long dummy);
75#endif
76
77#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
78#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
79
80/*
81 * These can be toggled for performance analysis, otherwise use default.
82 */
83#define CONFIG_L2_CACHE /* toggle L2 cache */
84#define CONFIG_BTB /* toggle branch predition */
85#define CONFIG_ENABLE_36BIT_PHYS 1
86
87/*
88 * Base addresses -- Note these are effective addresses where the
89 * actual resources get mapped (not physical addresses)
90 */
91#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
92#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
93#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
94#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
95#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
96#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
97
98/*
99 * Diagnostics
100 */
101#define CONFIG_SYS_ALT_MEMTEST
102#define CONFIG_SYS_MEMTEST_START 0x10000000
103#define CONFIG_SYS_MEMTEST_END 0x20000000
104
105/*
106 * Memory map
107 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
108 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
109 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
110 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
111 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
112 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
113 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
114 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
115 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
116 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
117 */
118
Kumar Gala68f9c1e2009-09-15 22:21:58 -0500[diff] [blame^]119#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]120
121/*
122 * NAND flash configuration
123 */
124#define CONFIG_SYS_NAND_BASE 0xef800000
125#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500[diff] [blame]126#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
127 CONFIG_SYS_NAND_BASE2}
128#define CONFIG_SYS_MAX_NAND_DEVICE 2
129#define CONFIG_MTD_NAND_VERIFY_WRITE
130#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
131#define CONFIG_NAND_FSL_ELBC
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]132
133/*
134 * NOR flash configuration
135 */
136#define CONFIG_SYS_FLASH_BASE 0xf8000000
137#define CONFIG_SYS_FLASH_BASE2 0xf0000000
138#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
139#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
140#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
141#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
142#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
143#define CONFIG_FLASH_CFI_DRIVER
144#define CONFIG_SYS_FLASH_CFI
Peter Tyser5ff82102009-07-19 19:17:40 -0500[diff] [blame]145#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]146#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
147 {0xf7f40000, 0xc0000} }
148#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
149
150/*
151 * Chip select configuration
152 */
153/* NOR Flash 0 on CS0 */
154#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
155 BR_PS_16 | \
156 BR_V)
157#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
158 OR_GPCM_CSNT | \
159 OR_GPCM_XACS | \
160 OR_GPCM_ACS_DIV2 | \
161 OR_GPCM_SCY_8 | \
162 OR_GPCM_TRLX | \
163 OR_GPCM_EHTR | \
164 OR_GPCM_EAD)
165
166/* NOR Flash 1 on CS1 */
167#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
168 BR_PS_16 | \
169 BR_V)
170#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
171
172/* NAND flash on CS2 */
173#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
174 (2<<BR_DECC_SHIFT) | \
175 BR_PS_8 | \
176 BR_MS_FCM | \
177 BR_V)
178
179/* NAND flash on CS2 */
180#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
181 OR_FCM_PGS | \
182 OR_FCM_CSCT | \
183 OR_FCM_CST | \
184 OR_FCM_CHT | \
185 OR_FCM_SCY_1 | \
186 OR_FCM_TRLX | \
187 OR_FCM_EHTR)
188
189/* NAND flash on CS3 */
190#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
191 (2<<BR_DECC_SHIFT) | \
192 BR_PS_8 | \
193 BR_MS_FCM | \
194 BR_V)
195#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
196
197/*
198 * Use L1 as initial stack
199 */
200#define CONFIG_SYS_INIT_RAM_LOCK 1
201#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
202#define CONFIG_SYS_INIT_RAM_END 0x00004000
203
204#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
205#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
206#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
207
208#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
209#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
210
211/*
212 * Serial Port
213 */
214#define CONFIG_CONS_INDEX 1
215#define CONFIG_SYS_NS16550
216#define CONFIG_SYS_NS16550_SERIAL
217#define CONFIG_SYS_NS16550_REG_SIZE 1
218#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
219#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
220#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
221#define CONFIG_SYS_BAUDRATE_TABLE \
222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
223#define CONFIG_BAUDRATE 115200
224#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
225#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
226
227/*
228 * Use the HUSH parser
229 */
230#define CONFIG_SYS_HUSH_PARSER
231#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
232
233/*
234 * Pass open firmware flat tree
235 */
236#define CONFIG_OF_LIBFDT 1
237#define CONFIG_OF_BOARD_SETUP 1
238#define CONFIG_OF_STDOUT_VIA_ALIAS 1
239
240#define CONFIG_SYS_64BIT_VSPRINTF 1
241#define CONFIG_SYS_64BIT_STRTOUL 1
242
243/*
244 * I2C
245 */
246#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
247#define CONFIG_HARD_I2C /* I2C with hardware support */
248#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
249#define CONFIG_SYS_I2C_SLAVE 0x7F
250#define CONFIG_SYS_I2C_OFFSET 0x3000
251#define CONFIG_SYS_I2C2_OFFSET 0x3100
252#define CONFIG_I2C_MULTI_BUS
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]253
254/* PEX8518 slave I2C interface */
255#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
256
257/* I2C DS1631 temperature sensor */
258#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
259#define CONFIG_DTT_DS1621
260#define CONFIG_DTT_SENSORS { 0 }
261
262/* I2C EEPROM - AT24C128B */
263#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
264#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
265#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
266#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
267
268/* I2C RTC */
269#define CONFIG_RTC_M41T11 1
270#define CONFIG_SYS_I2C_RTC_ADDR 0x68
271#define CONFIG_SYS_M41T11_BASE_YEAR 2000
272
273/* GPIO/EEPROM/SRAM */
274#define CONFIG_DS4510
275#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
276
277/* GPIO */
278#define CONFIG_PCA953X
279#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
280#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
281#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
282#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
283#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
284
285/*
286 * PU = pulled high, PD = pulled low
287 * I = input, O = output, IO = input/output
288 */
289/* PCA9557 @ 0x18*/
290#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
291#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
292#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
293#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
294#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
295#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
296#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
297#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
298
299/* PCA9557 @ 0x1c*/
300#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
301#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
302#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
303#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
304#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
305#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
306#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
307#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
308
309/* PCA9557 @ 0x1e*/
310#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
311#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
312#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
313#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
314#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
315#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
316#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
317
318/* PCA9557 @ 0x1f */
319#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
320#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
321#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
322#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
323#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
324
325/*
326 * General PCI
327 * Memory space is mapped 1-1, but I/O space must start from 0.
328 */
329/* PCIE1 - VPX P1 */
330#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
331#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
332#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
333#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
334#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
335#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
336
337/* PCIE2 - PEX8518 */
338#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
339#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
340#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
341#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
342#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
343#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
344
345/*
346 * Networking options
347 */
348#define CONFIG_TSEC_ENET /* tsec ethernet support */
349#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
350#define CONFIG_NET_MULTI 1
351#define CONFIG_TSEC_TBI
352#define CONFIG_MII 1 /* MII PHY management */
353#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
354#define CONFIG_ETHPRIME "eTSEC2"
355
356#define CONFIG_TSEC1 1
357#define CONFIG_TSEC1_NAME "eTSEC1"
358#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
359#define TSEC1_PHY_ADDR 1
360#define TSEC1_PHYIDX 0
361#define CONFIG_HAS_ETH0
362
363#define CONFIG_TSEC2 1
364#define CONFIG_TSEC2_NAME "eTSEC2"
365#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
366#define TSEC2_PHY_ADDR 2
367#define TSEC2_PHYIDX 0
368#define CONFIG_HAS_ETH1
369
370/*
371 * Command configuration.
372 */
373#include <config_cmd_default.h>
374
375#define CONFIG_CMD_ASKENV
376#define CONFIG_CMD_DATE
377#define CONFIG_CMD_DHCP
378#define CONFIG_CMD_DS4510
379#define CONFIG_CMD_DS4510_INFO
380#define CONFIG_CMD_DTT
381#define CONFIG_CMD_EEPROM
382#define CONFIG_CMD_ELF
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]383#define CONFIG_CMD_FLASH
384#define CONFIG_CMD_I2C
385#define CONFIG_CMD_JFFS2
386#define CONFIG_CMD_MII
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500[diff] [blame]387#define CONFIG_CMD_NAND
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]388#define CONFIG_CMD_NET
389#define CONFIG_CMD_PCA953X
390#define CONFIG_CMD_PCA953X_INFO
391#define CONFIG_CMD_PCI
392#define CONFIG_CMD_PING
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500[diff] [blame]393#define CONFIG_CMD_SAVEENV
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]394#define CONFIG_CMD_SNTP
395
396/*
397 * Miscellaneous configurable options
398 */
399#define CONFIG_SYS_LONGHELP /* undef to save memory */
400#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
401#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
402#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
403#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
404#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
405#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
406#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
407#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
408#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
409#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
410#define CONFIG_PANIC_HANG /* do not reset board on panic */
411#define CONFIG_PREBOOT /* enable preboot variable */
412#define CONFIG_FIT 1
413#define CONFIG_FIT_VERBOSE 1
414#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
415
416/*
417 * For booting Linux, the board info and command line data
418 * have to be in the first 16 MB of memory, since this is
419 * the maximum mapped by the Linux kernel during initialization.
420 */
421#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500[diff] [blame]422#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600[diff] [blame]423
424/*
425 * Boot Flags
426 */
427#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
428#define BOOTFLAG_WARM 0x02 /* Software reboot */
429
430/*
431 * Environment Configuration
432 */
433#define CONFIG_ENV_IS_IN_FLASH 1
434#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
435#define CONFIG_ENV_SIZE 0x8000
436#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
437
438/*
439 * Flash memory map:
440 * fff80000 - ffffffff Pri U-Boot (512 KB)
441 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
442 * fff00000 - fff3ffff Pri FDT (256KB)
443 * fef00000 - ffefffff Pri OS image (16MB)
444 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
445 *
446 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
447 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
448 * f7f00000 - f7f3ffff Sec FDT (256KB)
449 * f6f00000 - f7efffff Sec OS image (16MB)
450 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
451 */
452#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
453#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
454#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
455#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
456#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
457#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
458
459#define CONFIG_PROG_UBOOT1 \
460 "$download_cmd $loadaddr $ubootfile; " \
461 "if test $? -eq 0; then " \
462 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
463 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
464 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
465 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
466 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
467 "if test $? -ne 0; then " \
468 "echo PROGRAM FAILED; " \
469 "else; " \
470 "echo PROGRAM SUCCEEDED; " \
471 "fi; " \
472 "else; " \
473 "echo DOWNLOAD FAILED; " \
474 "fi;"
475
476#define CONFIG_PROG_UBOOT2 \
477 "$download_cmd $loadaddr $ubootfile; " \
478 "if test $? -eq 0; then " \
479 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
480 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
481 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
482 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
483 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
484 "if test $? -ne 0; then " \
485 "echo PROGRAM FAILED; " \
486 "else; " \
487 "echo PROGRAM SUCCEEDED; " \
488 "fi; " \
489 "else; " \
490 "echo DOWNLOAD FAILED; " \
491 "fi;"
492
493#define CONFIG_BOOT_OS_NET \
494 "$download_cmd $osaddr $osfile; " \
495 "if test $? -eq 0; then " \
496 "if test -n $fdtaddr; then " \
497 "$download_cmd $fdtaddr $fdtfile; " \
498 "if test $? -eq 0; then " \
499 "bootm $osaddr - $fdtaddr; " \
500 "else; " \
501 "echo FDT DOWNLOAD FAILED; " \
502 "fi; " \
503 "else; " \
504 "bootm $osaddr; " \
505 "fi; " \
506 "else; " \
507 "echo OS DOWNLOAD FAILED; " \
508 "fi;"
509
510#define CONFIG_PROG_OS1 \
511 "$download_cmd $osaddr $osfile; " \
512 "if test $? -eq 0; then " \
513 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
514 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
515 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
516 "if test $? -ne 0; then " \
517 "echo OS PROGRAM FAILED; " \
518 "else; " \
519 "echo OS PROGRAM SUCCEEDED; " \
520 "fi; " \
521 "else; " \
522 "echo OS DOWNLOAD FAILED; " \
523 "fi;"
524
525#define CONFIG_PROG_OS2 \
526 "$download_cmd $osaddr $osfile; " \
527 "if test $? -eq 0; then " \
528 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
529 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
530 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
531 "if test $? -ne 0; then " \
532 "echo OS PROGRAM FAILED; " \
533 "else; " \
534 "echo OS PROGRAM SUCCEEDED; " \
535 "fi; " \
536 "else; " \
537 "echo OS DOWNLOAD FAILED; " \
538 "fi;"
539
540#define CONFIG_PROG_FDT1 \
541 "$download_cmd $fdtaddr $fdtfile; " \
542 "if test $? -eq 0; then " \
543 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
544 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
545 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
546 "if test $? -ne 0; then " \
547 "echo FDT PROGRAM FAILED; " \
548 "else; " \
549 "echo FDT PROGRAM SUCCEEDED; " \
550 "fi; " \
551 "else; " \
552 "echo FDT DOWNLOAD FAILED; " \
553 "fi;"
554
555#define CONFIG_PROG_FDT2 \
556 "$download_cmd $fdtaddr $fdtfile; " \
557 "if test $? -eq 0; then " \
558 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
559 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
560 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
561 "if test $? -ne 0; then " \
562 "echo FDT PROGRAM FAILED; " \
563 "else; " \
564 "echo FDT PROGRAM SUCCEEDED; " \
565 "fi; " \
566 "else; " \
567 "echo FDT DOWNLOAD FAILED; " \
568 "fi;"
569
570#define CONFIG_EXTRA_ENV_SETTINGS \
571 "autoload=yes\0" \
572 "download_cmd=tftp\0" \
573 "console_args=console=ttyS0,115200\0" \
574 "root_args=root=/dev/nfs rw\0" \
575 "misc_args=ip=on\0" \
576 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
577 "bootfile=/home/user/file\0" \
578 "osfile=/home/user/uImage-XPedite5370\0" \
579 "fdtfile=/home/user/xpedite5370.dtb\0" \
580 "ubootfile=/home/user/u-boot.bin\0" \
581 "fdtaddr=c00000\0" \
582 "osaddr=0x1000000\0" \
583 "loadaddr=0x1000000\0" \
584 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
585 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
586 "prog_os1="CONFIG_PROG_OS1"\0" \
587 "prog_os2="CONFIG_PROG_OS2"\0" \
588 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
589 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
590 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
591 "bootcmd_flash1=run set_bootargs; " \
592 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
593 "bootcmd_flash2=run set_bootargs; " \
594 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
595 "bootcmd=run bootcmd_flash1\0"
596#endif /* __CONFIG_H */