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gerrit.cesnet.cz / github / trini / u-boot / 68ebc7c86b5ecbbf60360c98b81e8aee8e774944 / . / drivers / clk / adi / clk-adi-sc58x.c
blob: 05a0feddec7aaf62d3039fc49fcf9502ec1acf96 [file] [log] [blame]
Tom Rini03de3052024-05-20 13:35:03 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * (C) Copyright 2022 - Analog Devices, Inc.
4 *
5 * Written and/or maintained by Timesys Corporation
6 *
7 * Author: Greg Malysa <greg.malysa@timesys.com>
8 *
9 * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
10 */
11
12#include <clk.h>
13#include <clk-uclass.h>
14#include <dm.h>
15#include <dt-bindings/clock/adi-sc5xx-clock.h>
16#include <linux/compiler_types.h>
17#include <linux/clk-provider.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/printk.h>
21#include <linux/types.h>
22
23#include "clk.h"
24
25static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
26static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
27static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
28static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"};
29static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
30static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dummy"};
31static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"};
32static const char * const reserved_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"};
33static const char * const gige_sels[] = {"sclk0_0", "sclk1_1", "cclk0_1", "oclk_0"};
34static const char * const lp_sels[] = {"sclk0_0", "sclk0_1", "cclk1_1", "dclk_1"};
35static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1",
36 "dclk_1"};
37
38static int sc58x_clock_probe(struct udevice *dev)
39{
40 void __iomem *cgu0;
41 void __iomem *cgu1;
42 void __iomem *cdu;
43 int ret;
44 struct resource res;
45
46 struct clk *clks[ADSP_SC58X_CLK_END];
47 struct clk dummy, clkin0, clkin1;
48
49 ret = dev_read_resource_byname(dev, "cgu0", &res);
50 if (ret)
51 return ret;
52 cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
53
54 ret = dev_read_resource_byname(dev, "cgu1", &res);
55 if (ret)
56 return ret;
57 cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
58
59 ret = dev_read_resource_byname(dev, "cdu", &res);
60 if (ret)
61 return ret;
62 cdu = devm_ioremap(dev, res.start, resource_size(&res));
63
64 // Input clock configuration
65 clk_get_by_name(dev, "dummy", &dummy);
66 clk_get_by_name(dev, "sys_clkin0", &clkin0);
67 clk_get_by_name(dev, "sys_clkin1", &clkin1);
68
69 clks[ADSP_SC58X_CLK_DUMMY] = &dummy;
70 clks[ADSP_SC58X_CLK_SYS_CLKIN0] = &clkin0;
71 clks[ADSP_SC58X_CLK_SYS_CLKIN1] = &clkin1;
72
73 clks[ADSP_SC58X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
74 2, CLK_SET_RATE_PARENT,
75 cdu + CDU_CLKINSEL, 0, 1, 0);
76
77 // CGU configuration and internal clocks
78 clks[ADSP_SC58X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
79 "sys_clkin0",
80 CLK_SET_RATE_PARENT,
81 cgu0 + CGU_CTL, 0, 1, 0);
82 clks[ADSP_SC58X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
83 "cgu1_in_sel",
84 CLK_SET_RATE_PARENT,
85 cgu1 + CGU_CTL, 0, 1, 0);
86
87 // VCO output inside PLL
88 clks[ADSP_SC58X_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df",
89 cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
90 CGU_MSEL_WIDTH, 0, false);
91 clks[ADSP_SC58X_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df",
92 cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
93 CGU_MSEL_WIDTH, 0, false);
94
95 // Final PLL output
96 clks[ADSP_SC58X_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk",
97 "cgu0_vco",
98 CLK_SET_RATE_PARENT,
99 1, 1);
100 clks[ADSP_SC58X_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk",
101 "cgu1_vco",
102 CLK_SET_RATE_PARENT,
103 1, 1);
104
105 // Dividers from pll output
106 clks[ADSP_SC58X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
107 cgu0 + CGU_DIV, 0, 5, 0);
108 clks[ADSP_SC58X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
109 cgu0 + CGU_DIV, 8, 5, 0);
110 clks[ADSP_SC58X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
111 cgu0 + CGU_DIV, 16, 5, 0);
112 clks[ADSP_SC58X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
113 cgu0 + CGU_DIV, 22, 7, 0);
114 clks[ADSP_SC58X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
115 cgu0 + CGU_DIV, 5, 3, 0);
116 clks[ADSP_SC58X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
117 cgu0 + CGU_DIV, 13, 3, 0);
118
119 clks[ADSP_SC58X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
120 cgu1 + CGU_DIV, 0, 5, 0);
121 clks[ADSP_SC58X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
122 cgu1 + CGU_DIV, 8, 5, 0);
123 clks[ADSP_SC58X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
124 cgu1 + CGU_DIV, 16, 5, 0);
125 clks[ADSP_SC58X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
126 cgu1 + CGU_DIV, 22, 7, 0);
127 clks[ADSP_SC58X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1",
128 cgu1 + CGU_DIV, 5, 3, 0);
129 clks[ADSP_SC58X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1",
130 cgu1 + CGU_DIV, 13, 3, 0);
131
132 // Gates to enable CGU outputs
133 clks[ADSP_SC58X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
134 cgu0 + CGU_CCBF_DIS, 0);
135 clks[ADSP_SC58X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv",
136 cgu1 + CGU_CCBF_DIS, 1);
137 clks[ADSP_SC58X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
138 cgu0 + CGU_SCBF_DIS, 3);
139 clks[ADSP_SC58X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
140 cgu0 + CGU_SCBF_DIS, 2);
141 clks[ADSP_SC58X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv",
142 cgu0 + CGU_SCBF_DIS, 1);
143 clks[ADSP_SC58X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
144 cgu0 + CGU_SCBF_DIS, 0);
145
146 clks[ADSP_SC58X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
147 cgu1 + CGU_CCBF_DIS, 0);
148 clks[ADSP_SC58X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv",
149 cgu1 + CGU_CCBF_DIS, 1);
150 clks[ADSP_SC58X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
151 cgu1 + CGU_SCBF_DIS, 3);
152 clks[ADSP_SC58X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
153 cgu1 + CGU_SCBF_DIS, 2);
154 clks[ADSP_SC58X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv",
155 cgu1 + CGU_SCBF_DIS, 1);
156 clks[ADSP_SC58X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv",
157 cgu1 + CGU_SCBF_DIS, 0);
158
159 // Extra half rate clocks generated in the CDU
160 clks[ADSP_SC58X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half",
161 "oclk_0",
162 CLK_SET_RATE_PARENT,
163 1, 2);
164 clks[ADSP_SC58X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL,
165 "cclk1_1_half",
166 "cclk1_1",
167 CLK_SET_RATE_PARENT,
168 1, 2);
169
170 // CDU output muxes
171 clks[ADSP_SC58X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
172 sharc0_sels);
173 clks[ADSP_SC58X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
174 sharc1_sels);
175 clks[ADSP_SC58X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
176 clks[ADSP_SC58X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
177 cdu_ddr_sels);
178 clks[ADSP_SC58X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
179 clks[ADSP_SC58X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
180 clks[ADSP_SC58X_CLK_RESERVED_SEL] = cdu_mux("reserved_sel", cdu + CDU_CFG6,
181 reserved_sels);
182 clks[ADSP_SC58X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
183 clks[ADSP_SC58X_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels);
184 clks[ADSP_SC58X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels);
185
186 // CDU output enable gates
187 clks[ADSP_SC58X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0,
188 CLK_IS_CRITICAL);
189 clks[ADSP_SC58X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1,
190 CLK_IS_CRITICAL);
191 clks[ADSP_SC58X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
192 CLK_IS_CRITICAL);
193 clks[ADSP_SC58X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3,
194 CLK_IS_CRITICAL);
195 clks[ADSP_SC58X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
196 clks[ADSP_SC58X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
197 clks[ADSP_SC58X_CLK_RESERVED] = cdu_gate("reserved", "reserved_sel",
198 cdu + CDU_CFG6, 0);
199 clks[ADSP_SC58X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
200 clks[ADSP_SC58X_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0);
201 clks[ADSP_SC58X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0);
202
203 ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
204 if (ret)
205 pr_err("CDU error detected\n");
206
207 return ret;
208}
209
210static const struct udevice_id adi_sc58x_clk_ids[] = {
211 { .compatible = "adi,sc58x-clocks" },
212 { },
213};
214
215U_BOOT_DRIVER(adi_sc58x_clk) = {
216 .name = "clk_adi_sc58x",
217 .id = UCLASS_CLK,
218 .of_match = adi_sc58x_clk_ids,
219 .ops = &adi_clk_ops,
220 .probe = sc58x_clock_probe,
221 .flags = DM_FLAG_PRE_RELOC,
222};