Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 68620c9698f109c1f001f80d282138a5c67cabef / . / drivers / clk / sunxi / clk_h3.c
blob: f5ae1e95559c725c5148b1d96999987174d04e76 [file] [log] [blame]
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-h3-ccu.h>
13#include <dt-bindings/reset/sun8i-h3-ccu.h>
14
15static struct ccu_clk_gate h3_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki68620c92019-02-28 00:26:57 +0530[diff] [blame^]19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
26 [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
27 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
28 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
29 [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
30 [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
31
Jagan Teki4acc7112018-12-30 21:29:24 +0530[diff] [blame]32 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
33 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
34 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
35 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
36
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]37 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
38 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
39
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]40 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
41 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
42 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
43 [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
44 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
45 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
46 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
47 [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
48};
49
50static struct ccu_reset h3_resets[] = {
51 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
52 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
53 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
54 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
55
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]56 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
57 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
58 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki68620c92019-02-28 00:26:57 +0530[diff] [blame^]59 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]60 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
61 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]62 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
63 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
64 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
65 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
66 [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
67 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
68 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
69 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
70 [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]71
72 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
73 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
74 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
75 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]76};
77
78static const struct ccu_desc h3_ccu_desc = {
79 .gates = h3_gates,
80 .resets = h3_resets,
81};
82
83static int h3_clk_bind(struct udevice *dev)
84{
85 return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
86}
87
88static const struct udevice_id h3_ccu_ids[] = {
89 { .compatible = "allwinner,sun8i-h3-ccu",
90 .data = (ulong)&h3_ccu_desc },
91 { .compatible = "allwinner,sun50i-h5-ccu",
92 .data = (ulong)&h3_ccu_desc },
93 { }
94};
95
96U_BOOT_DRIVER(clk_sun8i_h3) = {
97 .name = "sun8i_h3_ccu",
98 .id = UCLASS_CLK,
99 .of_match = h3_ccu_ids,
100 .priv_auto_alloc_size = sizeof(struct ccu_priv),
101 .ops = &sunxi_clk_ops,
102 .probe = sunxi_clk_probe,
103 .bind = h3_clk_bind,
104};