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Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +09001/*
2 * Configuation settings for the Hitachi Solution Engine 7720
3 *
4 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +09007 */
8
9#ifndef __MS7720SE_H
10#define __MS7720SE_H
11
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090012#define CONFIG_SH 1
13#define CONFIG_SH3 1
14#define CONFIG_CPU_SH7720 1
15#define CONFIG_MS7720SE 1
16
17#define CONFIG_CMD_FLASH
Mike Frysingerbdab39d2009-01-28 19:08:14 -050018#define CONFIG_CMD_SAVEENV
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090019#define CONFIG_CMD_SDRAM
20#define CONFIG_CMD_MEMORY
21#define CONFIG_CMD_CACHE
22#define CONFIG_CMD_PCMCIA
23#define CONFIG_CMD_IDE
24#define CONFIG_CMD_EXT2
25
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090026#define CONFIG_BAUDRATE 115200
27#define CONFIG_BOOTARGS "console=ttySC0,115200"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +000028#define CONFIG_BOOTFILE "/boot/zImage"
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090029#define CONFIG_LOADADDR 0x8E000000
30
31#define CONFIG_VERSION_VARIABLE
32#undef CONFIG_SHOW_BOOT_PROGRESS
33
34/* MEMORY */
35#define MS7720SE_SDRAM_BASE 0x8C000000
36#define MS7720SE_FLASH_BASE_1 0xA0000000
37#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
38
Nobuhiro Iwamatsu46198752011-01-17 21:05:35 +090039#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_LONGHELP /* undef to save memory */
41#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
42#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
43#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
44#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090045/* Buffer size for Boot Arguments passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_BARGSIZE 512
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090047/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090049
50/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020051#define CONFIG_SCIF_CONSOLE 1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090052#define CONFIG_CONS_SCIF0 1
53
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
55#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090056
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
58#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
61#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
62#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
63#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090065
66
67/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020069#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#undef CONFIG_SYS_FLASH_QUIET_TEST
71#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090072
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090074
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MAX_FLASH_SECT 150
76#define CONFIG_SYS_MAX_FLASH_BANKS 1
77#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090078
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020079#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020080#define CONFIG_ENV_SECT_SIZE (64 * 1024)
81#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
83#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
84#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090085
86/* Board Clock */
87#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090088#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
89#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020090#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
Jean-Christophe PLAGNIOL-VILLARD8dd29c82009-06-04 12:06:47 +020091#define CONFIG_SYS_HZ 1000
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090092
93/* PCMCIA */
94#define CONFIG_IDE_PCMCIA 1
95#define CONFIG_MARUBUN_PCCARD 1
96#define CONFIG_PCMCIA_SLOT_A 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_IDE_MAXDEVICE 1
98#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
99#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
100#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
101#define CONFIG_SYS_MARUBUN_IO 0xb8600000
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +0900102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_PIO_MODE 1
104#define CONFIG_SYS_IDE_MAXBUS 1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +0900105#define CONFIG_DOS_PARTITION 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
107#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
108#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
109#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
110#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +0530111#define CONFIG_IDE_SWAP_IO
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +0900112
113#endif /* __MS7720SE_H */