blob: ad84ce38ede5ec12955c386ef847744676f2cec2 [file] [log] [blame]
Peng Fanc4cc2832019-12-30 17:39:18 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <clk-uclass.h>
10#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Peng Fanc4cc2832019-12-30 17:39:18 +080012#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <dt-bindings/clock/imx8mp-clock.h>
15
16#include "clk.h"
17
18#define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44};
45
46static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48};
49
50static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mp_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mp_drampll_tbl),
54};
55
56static struct imx_pll14xx_clk imx8mp_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mp_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
60};
61
62static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mp_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
66};
67
68static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
76 "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
77 "audio_pll1_out", "sys_pll3_out", };
78
79static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
80 "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
81 "video_pll1_out", "sys_pll1_100m",};
82
Ye Liac9a4512020-04-21 20:19:24 -070083static const char *imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
84 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
85 "video_pll1_out", "sys_pll3_out", };
86
Peng Fanc4cc2832019-12-30 17:39:18 +080087static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
88 "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
89 "sys_pll2_250m", "audio_pll1_out", };
90
91static const char *imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
92 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
93 "video_pll1_out", "audio_pll2_out", };
94
95static const char *imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
96 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
97 "video_pll1_out", "audio_pll2_out", };
98
99static const char *imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
100 "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
101 "audio_pll1_out", "video_pll1_out", };
102
103static const char *imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
104 "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
105 "audio_pll1_out", "sys_pll1_266m", };
106
107static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
108 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
109 "sys_pll2_250m", "audio_pll2_out", };
110
111static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
112 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
113 "audio_pll2_out", "sys_pll1_133m", };
114
115static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
116 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
117 "audio_pll2_out", "sys_pll1_133m", };
118
119static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
120 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
121 "audio_pll2_out", "sys_pll1_100m", };
122
123static const char *imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
124 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
125 "audio_pll2_out", "sys_pll1_100m", };
126
127static const char *imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
128 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
129 "audio_pll2_out", "sys_pll1_133m", };
130
131static const char *imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
132 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
133 "audio_pll2_out", "sys_pll1_133m", };
134
135static const char *imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
136 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
137 "audio_pll2_out", "sys_pll1_133m", };
138
139static const char *imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
140 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
141 "audio_pll2_out", "sys_pll1_133m", };
142
143static const char *imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
144 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
145 "clk_ext4", "audio_pll2_out", };
146
147static const char *imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
148 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
149 "clk_ext3", "audio_pll2_out", };
150
151static const char *imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
152 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
153 "clk_ext4", "audio_pll2_out", };
154
155static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
156 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
157 "clk_ext3", "audio_pll2_out", };
158
159static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
160 "sys_pll2_100m", "sys_pll1_800m",
161 "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
162
163static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
164 "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
165 "sys_pll1_80m", "sys_pll2_166m" };
166
Ye Liac9a4512020-04-21 20:19:24 -0700167static const char *imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
168 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
169 "sys_pll3_out", "sys_pll1_100m", };
170
Peng Fanc4cc2832019-12-30 17:39:18 +0800171static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
172 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
173 "audio_pll2_out", "sys_pll1_100m", };
174
Ye Liac9a4512020-04-21 20:19:24 -0700175static const char *imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
176 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
177 "video_pll1_out", "clk_ext4", };
178
179static const char *imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
180 "clk_ext1", "clk_ext2", "clk_ext3",
181 "clk_ext4", "video_pll1_out", };
182
183static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
184 "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
185 "video_pll1_out", "audio_pll2_out", };
186
Peng Fanc4cc2832019-12-30 17:39:18 +0800187static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
188
Peng Fanc4cc2832019-12-30 17:39:18 +0800189static int imx8mp_clk_probe(struct udevice *dev)
190{
191 void __iomem *base;
192
193 base = (void *)ANATOP_BASE_ADDR;
194
195 clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
196 clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
197 clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
198 clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
199 clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
200
201 clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
202 clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
203 clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
204 clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
205 clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
206
207 clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
208 clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
209 clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
210 clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
211 clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
212
213 clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
214 clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
215 clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
216 clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
217 clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
218
219 clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
220 clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
221 clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
222 clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
223 clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
224 clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
225 clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
226 clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
227 clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
228
229 clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
230 clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
231 clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
232 clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
233 clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
234 clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
235 clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
236 clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
237 clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
238
239 base = dev_read_addr_ptr(dev);
Sean Anderson082faeb2020-06-24 06:41:13 -0400240 if (!base)
Peng Fanc4cc2832019-12-30 17:39:18 +0800241 return -EINVAL;
242
243 clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
244 clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
245 clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
246
247 clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
Ye Liac9a4512020-04-21 20:19:24 -0700248 clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
Peng Fanc4cc2832019-12-30 17:39:18 +0800249 clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
250 clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
251 clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
252
253 clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
254
255 clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
256
257 clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
258 clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
259 clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
260 clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
Ye Liac9a4512020-04-21 20:19:24 -0700261 clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
262 clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
263 clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
264 clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
Peng Fanc4cc2832019-12-30 17:39:18 +0800265 clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
266 clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
267 clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
268 clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
269 clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
270 clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
271
272 clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
273 clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
274 clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
275 clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
276 clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
277
278 clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
279 clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
280
281 clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
282 clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
283
284 clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
Ye Liac9a4512020-04-21 20:19:24 -0700285
286 clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
Peng Fanc4cc2832019-12-30 17:39:18 +0800287 clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
288 clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
289 clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
290 clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
291 clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
292 clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
293 clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
294 clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
295 clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
Ye Liac9a4512020-04-21 20:19:24 -0700296 clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
Peng Fanc4cc2832019-12-30 17:39:18 +0800297 clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
298 clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
Ye Liac9a4512020-04-21 20:19:24 -0700299 clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
Peng Fanc4cc2832019-12-30 17:39:18 +0800300 clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
301 clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
302 clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
303 clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
304 clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
305 clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
306 clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
307 clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
308 clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
309
310 clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
311
312 return 0;
313}
314
315static const struct udevice_id imx8mp_clk_ids[] = {
316 { .compatible = "fsl,imx8mp-ccm" },
317 { },
318};
319
320U_BOOT_DRIVER(imx8mp_clk) = {
321 .name = "clk_imx8mp",
322 .id = UCLASS_CLK,
323 .of_match = imx8mp_clk_ids,
Sean Anderson682e73d2022-03-20 16:34:46 -0400324 .ops = &ccf_clk_ops,
Peng Fanc4cc2832019-12-30 17:39:18 +0800325 .probe = imx8mp_clk_probe,
326 .flags = DM_FLAG_PRE_RELOC,
327};