Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 1 | /* |
| 2 | * initcode.c - Initialize the processor. This is usually entails things |
| 3 | * like external memory, voltage regulators, etc... Note that this file |
| 4 | * cannot make any function calls as it may be executed all by itself by |
| 5 | * the Blackfin's bootrom in LDR format. |
| 6 | * |
| 7 | * Copyright (c) 2004-2008 Analog Devices Inc. |
| 8 | * |
| 9 | * Licensed under the GPL-2 or later. |
| 10 | */ |
| 11 | |
| 12 | #include <config.h> |
| 13 | #include <asm/blackfin.h> |
| 14 | #include <asm/mach-common/bits/bootrom.h> |
| 15 | #include <asm/mach-common/bits/ebiu.h> |
| 16 | #include <asm/mach-common/bits/pll.h> |
| 17 | #include <asm/mach-common/bits/uart.h> |
| 18 | |
| 19 | #define BFIN_IN_INITCODE |
| 20 | #include "serial.h" |
| 21 | |
| 22 | __attribute__((always_inline)) |
| 23 | static inline uint32_t serial_init(void) |
| 24 | { |
| 25 | #ifdef __ADSPBF54x__ |
| 26 | # ifdef BFIN_BOOT_UART_USE_RTS |
| 27 | # define BFIN_UART_USE_RTS 1 |
| 28 | # else |
| 29 | # define BFIN_UART_USE_RTS 0 |
| 30 | # endif |
| 31 | if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { |
| 32 | size_t i; |
| 33 | |
| 34 | /* force RTS rather than relying on auto RTS */ |
| 35 | bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL); |
| 36 | |
| 37 | /* Wait for the line to clear up. We cannot rely on UART |
| 38 | * registers as none of them reflect the status of the RSR. |
| 39 | * Instead, we'll sleep for ~10 bit times at 9600 baud. |
| 40 | * We can precalc things here by assuming boot values for |
| 41 | * PLL rather than loading registers and calculating. |
| 42 | * baud = SCLK / (16 ^ (1 - EDBO) * Divisor) |
| 43 | * EDB0 = 0 |
| 44 | * Divisor = (SCLK / baud) / 16 |
| 45 | * SCLK = baud * 16 * Divisor |
| 46 | * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5 |
| 47 | * CCLK = (16 * Divisor * 5) * (9600 / 10) |
| 48 | * In reality, this will probably be just about 1 second delay, |
| 49 | * so assuming 9600 baud is OK (both as a very low and too high |
| 50 | * speed as this will buffer things enough). |
| 51 | */ |
| 52 | #define _NUMBITS (10) /* how many bits to delay */ |
| 53 | #define _LOWBAUD (9600) /* low baud rate */ |
| 54 | #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */ |
| 55 | #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */ |
| 56 | #define _NUMINS (3) /* how many instructions in loop */ |
| 57 | #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS) |
| 58 | i = _CCLK; |
| 59 | while (i--) |
| 60 | asm volatile("" : : : "memory"); |
| 61 | } |
| 62 | #endif |
| 63 | |
Mike Frysinger | ee1d200 | 2008-10-20 21:08:54 -0400 | [diff] [blame] | 64 | uint32_t old_baud; |
| 65 | if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) |
| 66 | old_baud = serial_early_get_baud(); |
| 67 | else |
| 68 | old_baud = CONFIG_BAUDRATE; |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 69 | |
| 70 | if (BFIN_DEBUG_EARLY_SERIAL) { |
| 71 | serial_early_init(); |
| 72 | |
| 73 | /* If the UART is off, that means we need to program |
| 74 | * the baud rate ourselves initially. |
| 75 | */ |
| 76 | if (!old_baud) { |
| 77 | old_baud = CONFIG_BAUDRATE; |
| 78 | serial_early_set_baud(CONFIG_BAUDRATE); |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | return old_baud; |
| 83 | } |
| 84 | |
| 85 | __attribute__((always_inline)) |
| 86 | static inline void serial_deinit(void) |
| 87 | { |
| 88 | #ifdef __ADSPBF54x__ |
| 89 | if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { |
| 90 | /* clear forced RTS rather than relying on auto RTS */ |
| 91 | bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL); |
| 92 | } |
| 93 | #endif |
| 94 | } |
| 95 | |
| 96 | /* We need to reset the baud rate when we have early debug turned on |
| 97 | * or when we are booting over the UART. |
| 98 | * XXX: we should fix this to calc the old baud and restore it rather |
| 99 | * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have |
| 100 | * to figure out how to avoid the division in the baud calc ... |
| 101 | */ |
| 102 | __attribute__((always_inline)) |
| 103 | static inline void serial_reset_baud(uint32_t baud) |
| 104 | { |
| 105 | if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) |
| 106 | return; |
| 107 | |
| 108 | #ifndef CONFIG_LDR_LOAD_BAUD |
| 109 | # define CONFIG_LDR_LOAD_BAUD 115200 |
| 110 | #endif |
| 111 | |
| 112 | if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
| 113 | serial_early_set_baud(baud); |
| 114 | else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) |
| 115 | serial_early_set_baud(CONFIG_LDR_LOAD_BAUD); |
| 116 | else |
| 117 | serial_early_set_baud(CONFIG_BAUDRATE); |
| 118 | } |
| 119 | |
| 120 | __attribute__((always_inline)) |
| 121 | static inline void serial_putc(char c) |
| 122 | { |
| 123 | if (!BFIN_DEBUG_EARLY_SERIAL) |
| 124 | return; |
| 125 | |
| 126 | if (c == '\n') |
| 127 | *pUART_THR = '\r'; |
| 128 | |
| 129 | *pUART_THR = c; |
| 130 | |
| 131 | while (!(*pUART_LSR & TEMT)) |
| 132 | continue; |
| 133 | } |
| 134 | |
| 135 | |
| 136 | /* Max SCLK can be 133MHz ... dividing that by 4 gives |
| 137 | * us a freq of 33MHz for SPI which should generally be |
| 138 | * slow enough for the slow reads the bootrom uses. |
| 139 | */ |
| 140 | #ifndef CONFIG_SPI_BAUD_INITBLOCK |
| 141 | # define CONFIG_SPI_BAUD_INITBLOCK 4 |
| 142 | #endif |
| 143 | |
| 144 | /* PLL_DIV defines */ |
| 145 | #ifndef CONFIG_PLL_DIV_VAL |
| 146 | # if (CONFIG_CCLK_DIV == 1) |
| 147 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV1 |
| 148 | # elif (CONFIG_CCLK_DIV == 2) |
| 149 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV2 |
| 150 | # elif (CONFIG_CCLK_DIV == 4) |
| 151 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV4 |
| 152 | # elif (CONFIG_CCLK_DIV == 8) |
| 153 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV8 |
| 154 | # else |
| 155 | # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly |
| 156 | # endif |
| 157 | # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV) |
| 158 | #endif |
| 159 | |
| 160 | #ifndef CONFIG_PLL_LOCKCNT_VAL |
| 161 | # define CONFIG_PLL_LOCKCNT_VAL 0x0300 |
| 162 | #endif |
| 163 | |
| 164 | #ifndef CONFIG_PLL_CTL_VAL |
Mike Frysinger | 4f6a313 | 2008-06-01 01:26:29 -0400 | [diff] [blame] | 165 | # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF) |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 166 | #endif |
| 167 | |
| 168 | #ifndef CONFIG_EBIU_RSTCTL_VAL |
| 169 | # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ |
| 170 | #endif |
Mike Frysinger | 6761998 | 2008-10-11 21:46:52 -0400 | [diff] [blame^] | 171 | #if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) |
| 172 | # error invalid EBIU_RSTCTL value: must not set reserved bits |
| 173 | #endif |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 174 | |
| 175 | #ifndef CONFIG_EBIU_MBSCTL_VAL |
| 176 | # define CONFIG_EBIU_MBSCTL_VAL 0 |
| 177 | #endif |
| 178 | |
Mike Frysinger | 6761998 | 2008-10-11 21:46:52 -0400 | [diff] [blame^] | 179 | #if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) |
| 180 | # error invalid EBIU_DDRQUE value: must not set reserved bits |
| 181 | #endif |
| 182 | |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 183 | /* Make sure our voltage value is sane so we don't blow up! */ |
| 184 | #ifndef CONFIG_VR_CTL_VAL |
| 185 | # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) |
| 186 | # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) |
| 187 | # define CCLK_VLEV_120 400000000 |
| 188 | # define CCLK_VLEV_125 533000000 |
| 189 | # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) |
| 190 | # define CCLK_VLEV_120 401000000 |
| 191 | # define CCLK_VLEV_125 401000000 |
| 192 | # elif defined(__ADSPBF561__) |
| 193 | # define CCLK_VLEV_120 300000000 |
| 194 | # define CCLK_VLEV_125 501000000 |
| 195 | # endif |
| 196 | # if BFIN_CCLK < CCLK_VLEV_120 |
| 197 | # define CONFIG_VR_CTL_VLEV VLEV_120 |
| 198 | # elif BFIN_CCLK < CCLK_VLEV_125 |
| 199 | # define CONFIG_VR_CTL_VLEV VLEV_125 |
| 200 | # else |
| 201 | # define CONFIG_VR_CTL_VLEV VLEV_130 |
| 202 | # endif |
| 203 | # if defined(__ADSPBF52x__) /* TBD; use default */ |
| 204 | # undef CONFIG_VR_CTL_VLEV |
| 205 | # define CONFIG_VR_CTL_VLEV VLEV_110 |
| 206 | # elif defined(__ADSPBF54x__) /* TBD; use default */ |
| 207 | # undef CONFIG_VR_CTL_VLEV |
| 208 | # define CONFIG_VR_CTL_VLEV VLEV_120 |
Mike Frysinger | 622a8dc | 2008-10-11 21:54:00 -0400 | [diff] [blame] | 209 | # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */ |
| 210 | # undef CONFIG_VR_CTL_VLEV |
| 211 | # define CONFIG_VR_CTL_VLEV VLEV_125 |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 212 | # endif |
| 213 | |
| 214 | # ifdef CONFIG_BFIN_MAC |
| 215 | # define CONFIG_VR_CTL_CLKBUF CLKBUFOE |
| 216 | # else |
| 217 | # define CONFIG_VR_CTL_CLKBUF 0 |
| 218 | # endif |
| 219 | |
| 220 | # if defined(__ADSPBF52x__) |
| 221 | # define CONFIG_VR_CTL_FREQ FREQ_1000 |
| 222 | # else |
| 223 | # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000) |
| 224 | # endif |
| 225 | |
| 226 | # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ) |
| 227 | #endif |
| 228 | |
Mike Frysinger | 09dc6b0 | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 229 | BOOTROM_CALLED_FUNC_ATTR |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 230 | void initcode(ADI_BOOT_DATA *bootstruct) |
| 231 | { |
| 232 | uint32_t old_baud = serial_init(); |
| 233 | |
| 234 | #ifdef CONFIG_HW_WATCHDOG |
| 235 | # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE |
| 236 | # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000 |
| 237 | # endif |
| 238 | /* Program the watchdog with an initial timeout of ~20 seconds. |
| 239 | * Hopefully that should be long enough to load the u-boot LDR |
| 240 | * (from wherever) and then the common u-boot code can take over. |
| 241 | * In bypass mode, the start.S would have already set a much lower |
| 242 | * timeout, so don't clobber that. |
| 243 | */ |
| 244 | if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { |
| 245 | bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); |
| 246 | bfin_write_WDOG_CTL(0); |
| 247 | } |
| 248 | #endif |
| 249 | |
| 250 | serial_putc('S'); |
| 251 | |
| 252 | /* Blackfin bootroms use the SPI slow read opcode instead of the SPI |
| 253 | * fast read, so we need to slow down the SPI clock a lot more during |
| 254 | * boot. Once we switch over to u-boot's SPI flash driver, we'll |
| 255 | * increase the speed appropriately. |
| 256 | */ |
| 257 | if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
| 258 | #ifdef SPI0_BAUD |
| 259 | bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK); |
| 260 | #else |
| 261 | bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); |
| 262 | #endif |
| 263 | |
| 264 | serial_putc('B'); |
| 265 | |
| 266 | /* Disable all peripheral wakeups except for the PLL event. */ |
| 267 | #ifdef SIC_IWR0 |
| 268 | bfin_write_SIC_IWR0(1); |
| 269 | bfin_write_SIC_IWR1(0); |
| 270 | # ifdef SIC_IWR2 |
| 271 | bfin_write_SIC_IWR2(0); |
| 272 | # endif |
| 273 | #elif defined(SICA_IWR0) |
| 274 | bfin_write_SICA_IWR0(1); |
| 275 | bfin_write_SICA_IWR1(0); |
| 276 | #else |
| 277 | bfin_write_SIC_IWR(1); |
| 278 | #endif |
| 279 | |
Mike Frysinger | 09dc6b0 | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 280 | /* With newer bootroms, we use the helper function to set up |
| 281 | * the memory controller. Older bootroms lacks such helpers |
| 282 | * so we do it ourselves. |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 283 | */ |
Mike Frysinger | 09dc6b0 | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 284 | if (BOOTROM_CAPS_SYSCONTROL) { |
| 285 | serial_putc('S'); |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 286 | |
Mike Frysinger | 09dc6b0 | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 287 | ADI_SYSCTRL_VALUES memory_settings; |
| 288 | memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL; |
| 289 | memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL; |
| 290 | memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL; |
| 291 | memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL; |
| 292 | syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT | |
| 293 | (CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL); |
| 294 | } else { |
| 295 | serial_putc('L'); |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 296 | |
Mike Frysinger | 09dc6b0 | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 297 | bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 298 | |
Mike Frysinger | 09dc6b0 | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 299 | serial_putc('A'); |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 300 | |
Mike Frysinger | 09dc6b0 | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 301 | /* Only reprogram when needed to avoid triggering unnecessary |
| 302 | * PLL relock sequences. |
| 303 | */ |
| 304 | if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) { |
| 305 | serial_putc('!'); |
| 306 | bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); |
| 307 | asm("idle;"); |
| 308 | } |
| 309 | |
| 310 | serial_putc('C'); |
| 311 | |
| 312 | bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); |
| 313 | |
| 314 | serial_putc('K'); |
| 315 | |
| 316 | /* Only reprogram when needed to avoid triggering unnecessary |
| 317 | * PLL relock sequences. |
| 318 | */ |
| 319 | if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { |
| 320 | serial_putc('!'); |
| 321 | bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); |
| 322 | asm("idle;"); |
| 323 | } |
Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | /* Since we've changed the SCLK above, we may need to update |
| 327 | * the UART divisors (UART baud rates are based on SCLK). |
| 328 | */ |
| 329 | serial_reset_baud(old_baud); |
| 330 | |
| 331 | serial_putc('F'); |
| 332 | |
| 333 | /* Program the async banks controller. */ |
| 334 | bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); |
| 335 | bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); |
| 336 | bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); |
| 337 | |
| 338 | #ifdef EBIU_MODE |
| 339 | /* Not all parts have these additional MMRs. */ |
| 340 | bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); |
| 341 | bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); |
| 342 | bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); |
| 343 | #endif |
| 344 | |
| 345 | serial_putc('I'); |
| 346 | |
| 347 | /* Program the external memory controller. */ |
| 348 | #ifdef EBIU_RSTCTL |
| 349 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL); |
| 350 | bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL); |
| 351 | bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL); |
| 352 | bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL); |
| 353 | # ifdef CONFIG_EBIU_DDRCTL3_VAL |
| 354 | /* default is disable, so don't need to force this */ |
| 355 | bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL); |
| 356 | # endif |
| 357 | #else |
| 358 | bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); |
| 359 | bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL); |
| 360 | bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL); |
| 361 | #endif |
| 362 | |
| 363 | serial_putc('N'); |
| 364 | |
| 365 | /* Restore all peripheral wakeups. */ |
| 366 | #ifdef SIC_IWR0 |
| 367 | bfin_write_SIC_IWR0(-1); |
| 368 | bfin_write_SIC_IWR1(-1); |
| 369 | # ifdef SIC_IWR2 |
| 370 | bfin_write_SIC_IWR2(-1); |
| 371 | # endif |
| 372 | #elif defined(SICA_IWR0) |
| 373 | bfin_write_SICA_IWR0(-1); |
| 374 | bfin_write_SICA_IWR1(-1); |
| 375 | #else |
| 376 | bfin_write_SIC_IWR(-1); |
| 377 | #endif |
| 378 | |
| 379 | serial_putc('>'); |
| 380 | serial_putc('\n'); |
| 381 | |
| 382 | serial_deinit(); |
| 383 | } |