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wdenk42d1f032003-10-15 23:53:47 +00001/*
Andy Fleming151d5d92007-04-23 01:32:22 -05002 * Copyright 2004,2007 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30#include <command.h>
31#include <asm/cache.h>
32
Matthew McClintock40d5fa32006-06-28 10:43:36 -050033#if defined(CONFIG_OF_FLAT_TREE)
34#include <ft_build.h>
35#endif
36
wdenk42d1f032003-10-15 23:53:47 +000037
38int checkcpu (void)
39{
wdenk97d80fc2004-06-09 00:34:46 +000040 sys_info_t sysinfo;
41 uint lcrr; /* local bus clock ratio register */
42 uint clkdiv; /* clock divider portion of lcrr */
43 uint pvr, svr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050044 uint fam;
wdenk97d80fc2004-06-09 00:34:46 +000045 uint ver;
46 uint major, minor;
wdenk42d1f032003-10-15 23:53:47 +000047
wdenk97d80fc2004-06-09 00:34:46 +000048 svr = get_svr();
49 ver = SVR_VER(svr);
50 major = SVR_MAJ(svr);
51 minor = SVR_MIN(svr);
52
wdenk6c9e7892005-03-15 22:56:53 +000053 puts("CPU: ");
wdenk97d80fc2004-06-09 00:34:46 +000054 switch (ver) {
55 case SVR_8540:
56 puts("8540");
57 break;
58 case SVR_8541:
59 puts("8541");
60 break;
61 case SVR_8555:
62 puts("8555");
63 break;
64 case SVR_8560:
65 puts("8560");
66 break;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050067 case SVR_8548:
68 puts("8548");
69 break;
70 case SVR_8548_E:
71 puts("8548_E");
72 break;
Andy Fleming151d5d92007-04-23 01:32:22 -050073 case SVR_8544:
74 puts("8544");
75 break;
76 case SVR_8544_E:
77 puts("8544_E");
78 break;
Andy Fleming67431052007-04-23 02:54:25 -050079 case SVR_8568_E:
80 puts("8568_E");
81 break;
wdenk97d80fc2004-06-09 00:34:46 +000082 default:
83 puts("Unknown");
wdenk42d1f032003-10-15 23:53:47 +000084 break;
85 }
wdenk97d80fc2004-06-09 00:34:46 +000086 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +000087
wdenk6c9e7892005-03-15 22:56:53 +000088 pvr = get_pvr();
Jon Loeligerd9b94f22005-07-25 14:05:07 -050089 fam = PVR_FAM(pvr);
wdenk6c9e7892005-03-15 22:56:53 +000090 ver = PVR_VER(pvr);
91 major = PVR_MAJ(pvr);
92 minor = PVR_MIN(pvr);
93
94 printf("Core: ");
Jon Loeligerd9b94f22005-07-25 14:05:07 -050095 switch (fam) {
96 case PVR_FAM(PVR_85xx):
wdenk6c9e7892005-03-15 22:56:53 +000097 puts("E500");
98 break;
99 default:
100 puts("Unknown");
101 break;
102 }
103 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
104
wdenk97d80fc2004-06-09 00:34:46 +0000105 get_sys_info(&sysinfo);
106
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500107 puts("Clock Configuration:\n");
wdenk6c9e7892005-03-15 22:56:53 +0000108 printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
109 printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
110 printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
wdenk97d80fc2004-06-09 00:34:46 +0000111
112#if defined(CFG_LBC_LCRR)
113 lcrr = CFG_LBC_LCRR;
114#else
115 {
116 volatile immap_t *immap = (immap_t *)CFG_IMMR;
117 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
118
119 lcrr = lbc->lcrr;
120 }
121#endif
122 clkdiv = lcrr & 0x0f;
123 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
Andy Fleming151d5d92007-04-23 01:32:22 -0500124#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500125 /*
126 * Yes, the entire PQ38 family use the same
127 * bit-representation for twice the clock divider values.
128 */
129 clkdiv *= 2;
130#endif
wdenk97d80fc2004-06-09 00:34:46 +0000131 printf("LBC:%4lu MHz\n",
132 sysinfo.freqSystemBus / 1000000 / clkdiv);
133 } else {
wdenk6c9e7892005-03-15 22:56:53 +0000134 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
wdenk97d80fc2004-06-09 00:34:46 +0000135 }
136
137 if (ver == SVR_8560) {
wdenk6c9e7892005-03-15 22:56:53 +0000138 printf("CPM: %lu Mhz\n",
wdenk97d80fc2004-06-09 00:34:46 +0000139 sysinfo.freqSystemBus / 1000000);
140 }
141
wdenk6c9e7892005-03-15 22:56:53 +0000142 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000143
144 return 0;
145}
146
147
148/* ------------------------------------------------------------------------- */
149
150int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
151{
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800152 uint pvr;
153 uint ver;
154 pvr = get_pvr();
155 ver = PVR_VER(pvr);
156 if (ver & 1){
157 /* e500 v2 core has reset control register */
158 volatile unsigned int * rstcr;
159 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
160 *rstcr = 0x2; /* HRESET_REQ */
161 }else{
wdenk42d1f032003-10-15 23:53:47 +0000162 /*
163 * Initiate hard reset in debug control register DBCR0
164 * Make sure MSR[DE] = 1
165 */
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800166 unsigned long val;
167 val = mfspr(DBCR0);
168 val |= 0x70000000;
169 mtspr(DBCR0,val);
170 }
wdenk42d1f032003-10-15 23:53:47 +0000171 return 1;
172}
173
174
175/*
176 * Get timebase clock frequency
177 */
178unsigned long get_tbclk (void)
179{
180
181 sys_info_t sys_info;
182
183 get_sys_info(&sys_info);
wdenk2a8af182005-04-13 10:02:42 +0000184 return ((sys_info.freqSystemBus + 7L) / 8L);
wdenk42d1f032003-10-15 23:53:47 +0000185}
186
187
188#if defined(CONFIG_WATCHDOG)
189void
190watchdog_reset(void)
191{
192 int re_enable = disable_interrupts();
193 reset_85xx_watchdog();
194 if (re_enable) enable_interrupts();
195}
196
197void
198reset_85xx_watchdog(void)
199{
200 /*
201 * Clear TSR(WIS) bit by writing 1
202 */
203 unsigned long val;
Andy Fleming03b81b42007-04-23 01:44:44 -0500204 val = mfspr(SPRN_TSR);
205 val |= TSR_WIS;
206 mtspr(SPRN_TSR, val);
wdenk42d1f032003-10-15 23:53:47 +0000207}
208#endif /* CONFIG_WATCHDOG */
209
210#if defined(CONFIG_DDR_ECC)
wdenk42d1f032003-10-15 23:53:47 +0000211void dma_init(void) {
212 volatile immap_t *immap = (immap_t *)CFG_IMMR;
213 volatile ccsr_dma_t *dma = &immap->im_dma;
214
215 dma->satr0 = 0x02c40000;
216 dma->datr0 = 0x02c40000;
Andy Fleming03b81b42007-04-23 01:44:44 -0500217 dma->sr0 = 0xfffffff; /* clear any errors */
wdenk42d1f032003-10-15 23:53:47 +0000218 asm("sync; isync; msync");
219 return;
220}
221
222uint dma_check(void) {
223 volatile immap_t *immap = (immap_t *)CFG_IMMR;
224 volatile ccsr_dma_t *dma = &immap->im_dma;
225 volatile uint status = dma->sr0;
226
227 /* While the channel is busy, spin */
228 while((status & 4) == 4) {
229 status = dma->sr0;
230 }
231
Andy Fleming03b81b42007-04-23 01:44:44 -0500232 /* clear MR0[CS] channel start bit */
233 dma->mr0 &= 0x00000001;
234 asm("sync;isync;msync");
235
wdenk42d1f032003-10-15 23:53:47 +0000236 if (status != 0) {
237 printf ("DMA Error: status = %x\n", status);
238 }
239 return status;
240}
241
242int dma_xfer(void *dest, uint count, void *src) {
243 volatile immap_t *immap = (immap_t *)CFG_IMMR;
244 volatile ccsr_dma_t *dma = &immap->im_dma;
245
246 dma->dar0 = (uint) dest;
247 dma->sar0 = (uint) src;
248 dma->bcr0 = count;
249 dma->mr0 = 0xf000004;
250 asm("sync;isync;msync");
251 dma->mr0 = 0xf000005;
252 asm("sync;isync;msync");
253 return dma_check();
254}
255#endif
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500256
257
258#ifdef CONFIG_OF_FLAT_TREE
259void
260ft_cpu_setup(void *blob, bd_t *bd)
261{
262 u32 *p;
263 ulong clock;
264 int len;
265
266 clock = bd->bi_busfreq;
267 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
268 if (p != NULL)
269 *p = cpu_to_be32(clock);
270
Andy Fleming67431052007-04-23 02:54:25 -0500271 p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
272 if (p != NULL)
273 *p = cpu_to_be32(clock);
274
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500275 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
276 if (p != NULL)
277 *p = cpu_to_be32(clock);
278
279 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
280 if (p != NULL)
281 *p = cpu_to_be32(clock);
282
283#if defined(CONFIG_MPC85XX_TSEC1)
284 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
Timur Tabi85e7c7a2007-02-12 13:34:55 -0600285 if (p)
286 memcpy(p, bd->bi_enetaddr, 6);
287
288 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
289 if (p)
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500290 memcpy(p, bd->bi_enetaddr, 6);
291#endif
292
293#if defined(CONFIG_HAS_ETH1)
294 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
Timur Tabi85e7c7a2007-02-12 13:34:55 -0600295 if (p)
296 memcpy(p, bd->bi_enet1addr, 6);
297
298 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
299 if (p)
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500300 memcpy(p, bd->bi_enet1addr, 6);
301#endif
302
303#if defined(CONFIG_HAS_ETH2)
304 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
Timur Tabi85e7c7a2007-02-12 13:34:55 -0600305 if (p)
306 memcpy(p, bd->bi_enet2addr, 6);
307
308 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
309 if (p)
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500310 memcpy(p, bd->bi_enet2addr, 6);
311#endif
312
313#if defined(CONFIG_HAS_ETH3)
314 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
Timur Tabi85e7c7a2007-02-12 13:34:55 -0600315 if (p)
316 memcpy(p, bd->bi_enet3addr, 6);
317
318 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
319 if (p)
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500320 memcpy(p, bd->bi_enet3addr, 6);
321#endif
322
323}
324#endif