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Simon Glasse761ecd2013-04-17 16:13:36 +00001/*
2 * Copyright (c) 2012 The Chromium OS Authors.
3 *
Bin Meng076bb442014-11-09 22:19:13 +08004 * TSC calibration codes are adapted from Linux kernel
5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Simon Glasse761ecd2013-04-17 16:13:36 +00008 */
9
10#include <common.h>
11#include <malloc.h>
12#include <asm/io.h>
13#include <asm/i8254.h>
14#include <asm/ibmpc.h>
15#include <asm/msr.h>
16#include <asm/u-boot-x86.h>
17
Bin Meng076bb442014-11-09 22:19:13 +080018/* CPU reference clock frequency: in KHz */
19#define FREQ_83 83200
20#define FREQ_100 99840
21#define FREQ_133 133200
22#define FREQ_166 166400
23
24#define MAX_NUM_FREQS 8
25
Simon Glasse761ecd2013-04-17 16:13:36 +000026DECLARE_GLOBAL_DATA_PTR;
27
Bin Meng076bb442014-11-09 22:19:13 +080028/*
29 * According to Intel 64 and IA-32 System Programming Guide,
30 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
31 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
32 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
33 * so we need manually differentiate SoC families. This is what the
34 * field msr_plat does.
35 */
36struct freq_desc {
37 u8 x86_family; /* CPU family */
38 u8 x86_model; /* model */
Simon Glass5c1b6852014-11-12 22:42:04 -070039 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
40 u8 msr_plat;
Bin Meng076bb442014-11-09 22:19:13 +080041 u32 freqs[MAX_NUM_FREQS];
42};
43
44static struct freq_desc freq_desc_tables[] = {
45 /* PNW */
46 { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
47 /* CLV+ */
48 { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
49 /* TNG */
50 { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
51 /* VLV2 */
52 { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
Simon Glass5c1b6852014-11-12 22:42:04 -070053 /* Ivybridge */
54 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
Bin Meng076bb442014-11-09 22:19:13 +080055 /* ANN */
56 { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
57};
58
59static int match_cpu(u8 family, u8 model)
60{
61 int i;
62
63 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
64 if ((family == freq_desc_tables[i].x86_family) &&
65 (model == freq_desc_tables[i].x86_model))
66 return i;
67 }
68
69 return -1;
70}
71
72/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
73#define id_to_freq(cpu_index, freq_id) \
74 (freq_desc_tables[cpu_index].freqs[freq_id])
75
76/*
77 * Do MSR calibration only for known/supported CPUs.
78 *
79 * Returns the calibration value or 0 if MSR calibration failed.
80 */
Bin Meng3ba6a0f2015-01-06 22:14:14 +080081static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
Bin Meng076bb442014-11-09 22:19:13 +080082{
83 u32 lo, hi, ratio, freq_id, freq;
84 unsigned long res;
85 int cpu_index;
86
87 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
88 if (cpu_index < 0)
89 return 0;
90
91 if (freq_desc_tables[cpu_index].msr_plat) {
92 rdmsr(MSR_PLATFORM_INFO, lo, hi);
93 ratio = (lo >> 8) & 0x1f;
94 } else {
95 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
96 ratio = (hi >> 8) & 0x1f;
97 }
98 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
99
100 if (!ratio)
101 goto fail;
102
Simon Glass5c1b6852014-11-12 22:42:04 -0700103 if (freq_desc_tables[cpu_index].msr_plat == 2) {
104 /* TODO: Figure out how best to deal with this */
105 freq = FREQ_100;
106 debug("Using frequency: %u KHz\n", freq);
107 } else {
108 /* Get FSB FREQ ID */
109 rdmsr(MSR_FSB_FREQ, lo, hi);
110 freq_id = lo & 0x7;
111 freq = id_to_freq(cpu_index, freq_id);
112 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
113 freq_id, freq);
114 }
Bin Meng076bb442014-11-09 22:19:13 +0800115 if (!freq)
116 goto fail;
117
118 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
119 res = freq * ratio / 1000;
120 debug("TSC runs at %lu MHz\n", res);
121
122 return res;
123
124fail:
125 debug("Fast TSC calibration using MSR failed\n");
126 return 0;
127}
128
Bin Meng80de0492014-11-09 22:19:25 +0800129/*
130 * This reads the current MSB of the PIT counter, and
131 * checks if we are running on sufficiently fast and
132 * non-virtualized hardware.
133 *
134 * Our expectations are:
135 *
136 * - the PIT is running at roughly 1.19MHz
137 *
138 * - each IO is going to take about 1us on real hardware,
139 * but we allow it to be much faster (by a factor of 10) or
140 * _slightly_ slower (ie we allow up to a 2us read+counter
141 * update - anything else implies a unacceptably slow CPU
142 * or PIT for the fast calibration to work.
143 *
144 * - with 256 PIT ticks to read the value, we have 214us to
145 * see the same MSB (and overhead like doing a single TSC
146 * read per MSB value etc).
147 *
148 * - We're doing 2 reads per loop (LSB, MSB), and we expect
149 * them each to take about a microsecond on real hardware.
150 * So we expect a count value of around 100. But we'll be
151 * generous, and accept anything over 50.
152 *
153 * - if the PIT is stuck, and we see *many* more reads, we
154 * return early (and the next caller of pit_expect_msb()
155 * then consider it a failure when they don't see the
156 * next expected value).
157 *
158 * These expectations mean that we know that we have seen the
159 * transition from one expected value to another with a fairly
160 * high accuracy, and we didn't miss any events. We can thus
161 * use the TSC value at the transitions to calculate a pretty
162 * good value for the TSC frequencty.
163 */
164static inline int pit_verify_msb(unsigned char val)
165{
166 /* Ignore LSB */
167 inb(0x42);
168 return inb(0x42) == val;
169}
170
171static inline int pit_expect_msb(unsigned char val, u64 *tscp,
172 unsigned long *deltap)
173{
174 int count;
175 u64 tsc = 0, prev_tsc = 0;
176
177 for (count = 0; count < 50000; count++) {
178 if (!pit_verify_msb(val))
179 break;
180 prev_tsc = tsc;
181 tsc = rdtsc();
182 }
183 *deltap = rdtsc() - prev_tsc;
184 *tscp = tsc;
185
186 /*
187 * We require _some_ success, but the quality control
188 * will be based on the error terms on the TSC values.
189 */
190 return count > 5;
191}
192
193/*
194 * How many MSB values do we want to see? We aim for
195 * a maximum error rate of 500ppm (in practice the
196 * real error is much smaller), but refuse to spend
197 * more than 50ms on it.
198 */
199#define MAX_QUICK_PIT_MS 50
200#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
201
Bin Meng3ba6a0f2015-01-06 22:14:14 +0800202static unsigned long __maybe_unused quick_pit_calibrate(void)
Bin Meng80de0492014-11-09 22:19:25 +0800203{
204 int i;
205 u64 tsc, delta;
206 unsigned long d1, d2;
207
208 /* Set the Gate high, disable speaker */
209 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
210
211 /*
212 * Counter 2, mode 0 (one-shot), binary count
213 *
214 * NOTE! Mode 2 decrements by two (and then the
215 * output is flipped each time, giving the same
216 * final output frequency as a decrement-by-one),
217 * so mode 0 is much better when looking at the
218 * individual counts.
219 */
220 outb(0xb0, 0x43);
221
222 /* Start at 0xffff */
223 outb(0xff, 0x42);
224 outb(0xff, 0x42);
225
226 /*
227 * The PIT starts counting at the next edge, so we
228 * need to delay for a microsecond. The easiest way
229 * to do that is to just read back the 16-bit counter
230 * once from the PIT.
231 */
232 pit_verify_msb(0);
233
234 if (pit_expect_msb(0xff, &tsc, &d1)) {
235 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
236 if (!pit_expect_msb(0xff-i, &delta, &d2))
237 break;
238
239 /*
240 * Iterate until the error is less than 500 ppm
241 */
242 delta -= tsc;
243 if (d1+d2 >= delta >> 11)
244 continue;
245
246 /*
247 * Check the PIT one more time to verify that
248 * all TSC reads were stable wrt the PIT.
249 *
250 * This also guarantees serialization of the
251 * last cycle read ('d2') in pit_expect_msb.
252 */
253 if (!pit_verify_msb(0xfe - i))
254 break;
255 goto success;
256 }
257 }
258 debug("Fast TSC calibration failed\n");
259 return 0;
260
261success:
262 /*
263 * Ok, if we get here, then we've seen the
264 * MSB of the PIT decrement 'i' times, and the
265 * error has shrunk to less than 500 ppm.
266 *
267 * As a result, we can depend on there not being
268 * any odd delays anywhere, and the TSC reads are
269 * reliable (within the error).
270 *
271 * kHz = ticks / time-in-seconds / 1000;
272 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
273 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
274 */
275 delta *= PIT_TICK_RATE;
276 delta /= (i*256*1000);
277 debug("Fast TSC calibration using PIT\n");
278 return delta / 1000;
279}
280
Simon Glasse761ecd2013-04-17 16:13:36 +0000281void timer_set_base(u64 base)
282{
283 gd->arch.tsc_base = base;
284}
285
286/*
287 * Get the number of CPU time counter ticks since it was read first time after
288 * restart. This yields a free running counter guaranteed to take almost 6
289 * years to wrap around even at 100GHz clock rate.
290 */
Simon Glassd8819f92013-06-11 11:14:52 -0700291u64 __attribute__((no_instrument_function)) get_ticks(void)
Simon Glasse761ecd2013-04-17 16:13:36 +0000292{
293 u64 now_tick = rdtsc();
294
295 /* We assume that 0 means the base hasn't been set yet */
296 if (!gd->arch.tsc_base)
297 panic("No tick base available");
298 return now_tick - gd->arch.tsc_base;
299}
300
Simon Glasse761ecd2013-04-17 16:13:36 +0000301/* Get the speed of the TSC timer in MHz */
Simon Glassd8819f92013-06-11 11:14:52 -0700302unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
Simon Glasse761ecd2013-04-17 16:13:36 +0000303{
Bin Meng076bb442014-11-09 22:19:13 +0800304 unsigned long fast_calibrate;
Simon Glasse761ecd2013-04-17 16:13:36 +0000305
Bin Meng258b1352014-11-09 22:19:35 +0800306 if (gd->arch.tsc_mhz)
307 return gd->arch.tsc_mhz;
308
Bin Meng3ba6a0f2015-01-06 22:14:14 +0800309#ifdef CONFIG_TSC_CALIBRATION_BYPASS
310 fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ;
311#else
Bin Meng076bb442014-11-09 22:19:13 +0800312 fast_calibrate = try_msr_calibrate_tsc();
Simon Glass5c1b6852014-11-12 22:42:04 -0700313 if (!fast_calibrate) {
Bin Meng80de0492014-11-09 22:19:25 +0800314
Simon Glass5c1b6852014-11-12 22:42:04 -0700315 fast_calibrate = quick_pit_calibrate();
316 if (!fast_calibrate)
317 panic("TSC frequency is ZERO");
318 }
Bin Meng3ba6a0f2015-01-06 22:14:14 +0800319#endif
Bin Meng076bb442014-11-09 22:19:13 +0800320
Bin Meng258b1352014-11-09 22:19:35 +0800321 gd->arch.tsc_mhz = fast_calibrate;
Bin Meng076bb442014-11-09 22:19:13 +0800322 return fast_calibrate;
Simon Glasse761ecd2013-04-17 16:13:36 +0000323}
324
325unsigned long get_tbclk(void)
326{
327 return get_tbclk_mhz() * 1000 * 1000;
328}
329
330static ulong get_ms_timer(void)
331{
332 return (get_ticks() * 1000) / get_tbclk();
333}
334
335ulong get_timer(ulong base)
336{
337 return get_ms_timer() - base;
338}
339
Simon Glassd8819f92013-06-11 11:14:52 -0700340ulong __attribute__((no_instrument_function)) timer_get_us(void)
Simon Glasse761ecd2013-04-17 16:13:36 +0000341{
342 return get_ticks() / get_tbclk_mhz();
343}
344
345ulong timer_get_boot_us(void)
346{
347 return timer_get_us();
348}
349
350void __udelay(unsigned long usec)
351{
352 u64 now = get_ticks();
353 u64 stop;
354
355 stop = now + usec * get_tbclk_mhz();
356
357 while ((int64_t)(stop - get_ticks()) > 0)
358 ;
359}
360
361int timer_init(void)
362{
Simon Glassd0b6f242013-04-17 16:13:39 +0000363#ifdef CONFIG_SYS_PCAT_TIMER
364 /* Set up the PCAT timer if required */
365 pcat_timer_init();
366#endif
367
Simon Glasse761ecd2013-04-17 16:13:36 +0000368 return 0;
369}