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Phil Edworthy7fbeb642011-06-01 07:35:13 +01001/*
Phil Edworthyefa4e1b2011-06-09 16:22:43 +01002 * Configuation settings for the Renesas RSK2+SH7264 board
Phil Edworthy7fbeb642011-06-01 07:35:13 +01003 *
4 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Phil Edworthy7fbeb642011-06-01 07:35:13 +01009 */
10
11#ifndef __RSK7264_H
12#define __RSK7264_H
13
Phil Edworthy7fbeb642011-06-01 07:35:13 +010014#define CONFIG_CPU_SH7264 1
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010015#define CONFIG_RSK7264 1
Phil Edworthy7fbeb642011-06-01 07:35:13 +010016
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
18
Phil Edworthy7fbeb642011-06-01 07:35:13 +010019#define CONFIG_BOOTARGS "console=ttySC3,115200"
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010020#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
Phil Edworthy7fbeb642011-06-01 07:35:13 +010021
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010022#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010023#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
24#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
25#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010026
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010027/* Serial */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010028#define CONFIG_CONS_SCIF3 1
29
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010030/* Memory */
31/* u-boot relocated to top 256KB of ram */
32#define CONFIG_SYS_TEXT_BASE 0x0CFC0000
33#define CONFIG_SYS_SDRAM_BASE 0x0C000000
Phil Edworthy7fbeb642011-06-01 07:35:13 +010034#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
35
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010036#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
37#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010038#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010039#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
40#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010041
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010042/* Flash */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010043#define CONFIG_FLASH_CFI_DRIVER
44#define CONFIG_SYS_FLASH_CFI
45#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010046#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010047#define CONFIG_SYS_MAX_FLASH_BANKS 1
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010048#define CONFIG_SYS_MAX_FLASH_SECT 512
Phil Edworthy7fbeb642011-06-01 07:35:13 +010049
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010050#define CONFIG_ENV_OFFSET (128 * 1024)
51#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010052#define CONFIG_ENV_SECT_SIZE (128 * 1024)
53#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Phil Edworthy7fbeb642011-06-01 07:35:13 +010054
55/* Board Clock */
Phil Edworthy117029c2012-02-13 02:03:50 +000056#define CONFIG_SYS_CLK_FREQ 36000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090057#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
58#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010059#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsu8f0960e2014-01-08 14:57:30 +090060#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010061
62/* Network interface */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010063#define CONFIG_SMC911X
64#define CONFIG_SMC911X_16_BIT
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010065#define CONFIG_SMC911X_BASE 0x28000000
Phil Edworthy7fbeb642011-06-01 07:35:13 +010066
67#endif /* __RSK7264_H */