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Jon Loeliger3dd2db52007-10-16 13:54:01 -05001/*
Kumar Gala5e3d7052009-11-04 12:51:10 -06002 * Copyright 2007,2009 Freescale Semiconductor, Inc.
Jon Loeliger3dd2db52007-10-16 13:54:01 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
Jon Loeligerc9974ab2008-01-04 11:58:23 -060022
Jon Loeliger3dd2db52007-10-16 13:54:01 -050023#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/immap_86xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050028#include <asm/fsl_pci.h>
Jon Loeliger39aa1a72008-08-26 15:01:36 -050029#include <asm/fsl_ddr_sdram.h>
Jon Loeligerc9974ab2008-01-04 11:58:23 -060030#include <i2c.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050031#include <asm/io.h>
Jon Loeliger1df170f2008-01-04 12:07:27 -060032#include <libfdt.h>
33#include <fdt_support.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060034#include <spd_sdram.h>
Ben Warren89973f82008-08-31 22:22:04 -070035#include <netdev.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050036
37#include "../common/pixis.h"
38
Jon Loeliger3dd2db52007-10-16 13:54:01 -050039void sdram_init(void);
Becky Bruce4c77de32008-10-31 17:13:32 -050040phys_size_t fixed_sdram(void);
Jon Loeligerc9974ab2008-01-04 11:58:23 -060041void mpc8610hpcd_diu_init(void);
42
Jon Loeliger3dd2db52007-10-16 13:54:01 -050043
44/* called before any console output */
45int board_early_init_f(void)
46{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050048 volatile ccsr_gur_t *gur = &immap->im_gur;
49
York Suna8778802007-10-29 13:58:39 -050050 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
51
52 return 0;
53}
54
55int misc_init_r(void)
56{
57 u8 tmp_val, version;
Kumar Gala048e7ef2009-07-22 10:12:39 -050058 u8 *pixis_base = (u8 *)PIXIS_BASE;
York Suna8778802007-10-29 13:58:39 -050059
60 /*Do not use 8259PIC*/
Kumar Gala048e7ef2009-07-22 10:12:39 -050061 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
62 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
York Suna8778802007-10-29 13:58:39 -050063
64 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
Kumar Gala048e7ef2009-07-22 10:12:39 -050065 version = in_8(pixis_base + PIXIS_PVER);
York Suna8778802007-10-29 13:58:39 -050066 if(version >= 0x07) {
Kumar Gala048e7ef2009-07-22 10:12:39 -050067 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
68 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
York Suna8778802007-10-29 13:58:39 -050069 }
70
71 /* Using this for DIU init before the driver in linux takes over
72 * Enable the TFP410 Encoder (I2C address 0x38)
73 */
74
75 tmp_val = 0xBF;
76 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
77 /* Verify if enabled */
78 tmp_val = 0;
79 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
80 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
81
82 tmp_val = 0x10;
83 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
84 /* Verify if enabled */
85 tmp_val = 0;
86 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
87 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
88
89#ifdef CONFIG_FSL_DIU_FB
90 mpc8610hpcd_diu_init();
91#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -050092
93 return 0;
94}
95
96int checkboard(void)
97{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050099 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
Kumar Gala048e7ef2009-07-22 10:12:39 -0500100 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500101
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200102 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
103 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
Kumar Gala048e7ef2009-07-22 10:12:39 -0500104 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
105 in_8(pixis_base + PIXIS_PVER));
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500106
107 mcm->abcr |= 0x00010000; /* 0 */
108 mcm->hpmr3 = 0x80000008; /* 4c */
109 mcm->hpmr0 = 0;
110 mcm->hpmr1 = 0;
111 mcm->hpmr2 = 0;
112 mcm->hpmr4 = 0;
113 mcm->hpmr5 = 0;
114
115 return 0;
116}
117
118
Becky Bruce9973e3c2008-06-09 16:03:40 -0500119phys_size_t
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500120initdram(int board_type)
121{
Becky Bruce4c77de32008-10-31 17:13:32 -0500122 phys_size_t dram_size = 0;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500123
124#if defined(CONFIG_SPD_EEPROM)
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500125 dram_size = fsl_ddr_sdram();
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500126#else
127 dram_size = fixed_sdram();
128#endif
129
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500130 puts(" DDR: ");
131 return dram_size;
132}
133
134
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500135#if !defined(CONFIG_SPD_EEPROM)
136/*
137 * Fixed sdram init -- doesn't use serial presence detect.
138 */
139
Becky Bruce4c77de32008-10-31 17:13:32 -0500140phys_size_t fixed_sdram(void)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500141{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#if !defined(CONFIG_SYS_RAMBOOT)
143 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500144 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
145 uint d_init;
146
147 ddr->cs0_bnds = 0x0000001f;
148 ddr->cs0_config = 0x80010202;
149
Kumar Gala45239cf2008-04-29 10:27:08 -0500150 ddr->timing_cfg_3 = 0x00000000;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500151 ddr->timing_cfg_0 = 0x00260802;
152 ddr->timing_cfg_1 = 0x3935d322;
153 ddr->timing_cfg_2 = 0x14904cc8;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500154 ddr->sdram_mode = 0x00480432;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500155 ddr->sdram_mode_2 = 0x00000000;
156 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
157 ddr->sdram_data_init = 0xDEADBEEF;
158 ddr->sdram_clk_cntl = 0x03800000;
159 ddr->sdram_cfg_2 = 0x04400010;
160
161#if defined(CONFIG_DDR_ECC)
162 ddr->err_int_en = 0x0000000d;
163 ddr->err_disable = 0x00000000;
164 ddr->err_sbe = 0x00010000;
165#endif
166 asm("sync;isync");
167
168 udelay(500);
169
Peter Tysere7ee23e2009-07-17 10:14:45 -0500170 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500171
172
173#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
174 d_init = 1;
175 debug("DDR - 1st controller: memory initializing\n");
176 /*
177 * Poll until memory is initialized.
178 * 512 Meg at 400 might hit this 200 times or so.
179 */
180 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
181 udelay(1000);
182
183 debug("DDR: memory initialized\n\n");
184 asm("sync; isync");
185 udelay(500);
186#endif
187
188 return 512 * 1024 * 1024;
189#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500191}
192
193#endif
194
195#if defined(CONFIG_PCI)
196/*
197 * Initialize PCI Devices, report devices found.
198 */
199
200#ifndef CONFIG_PCI_PNP
201static struct pci_config_table pci_fsl86xxads_config_table[] = {
202 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
203 PCI_IDSEL_NUMBER, PCI_ANY_ID,
204 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
205 PCI_ENET0_MEMADDR,
206 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
207 {}
208};
209#endif
210
211
212static struct pci_controller pci1_hose = {
213#ifndef CONFIG_PCI_PNP
214config_table:pci_mpc86xxcts_config_table
215#endif
216};
217#endif /* CONFIG_PCI */
218
219#ifdef CONFIG_PCIE1
220static struct pci_controller pcie1_hose;
221#endif
222
223#ifdef CONFIG_PCIE2
224static struct pci_controller pcie2_hose;
225#endif
226
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500227void pci_init_board(void)
228{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500230 volatile ccsr_gur_t *gur = &immap->im_gur;
Kumar Gala5e3d7052009-11-04 12:51:10 -0600231 struct fsl_pci_info pci_info[3];
232 u32 devdisr, pordevsr, io_sel;
233 int first_free_busno = 0;
234 int num = 0;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500235
Kumar Gala5e3d7052009-11-04 12:51:10 -0600236 int pci_agent, pcie_ep, pcie_configured;
237
238 devdisr = in_be32(&gur->devdisr);
239 pordevsr = in_be32(&gur->pordevsr);
240 io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
241 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
242
243 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500244
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500245#ifdef CONFIG_PCIE1
Kumar Gala5e3d7052009-11-04 12:51:10 -0600246 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500247
Kumar Gala5e3d7052009-11-04 12:51:10 -0600248 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
249 SET_STD_PCIE_INFO(pci_info[num], 1);
250 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
251 printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
Peter Tyser64917ca2010-01-17 15:38:26 -0600252 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala5e3d7052009-11-04 12:51:10 -0600253 pci_info[num].regs);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500254
Kumar Gala5e3d7052009-11-04 12:51:10 -0600255 first_free_busno = fsl_pci_init_port(&pci_info[num++],
256 &pcie1_hose, first_free_busno);
257 } else {
258 printf (" PCIE1: disabled\n");
259 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500260
Kumar Gala5e3d7052009-11-04 12:51:10 -0600261 puts("\n");
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500262#else
Kumar Gala5e3d7052009-11-04 12:51:10 -0600263 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
264#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500265
266#ifdef CONFIG_PCIE2
Kumar Gala5e3d7052009-11-04 12:51:10 -0600267 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500268
Kumar Gala5e3d7052009-11-04 12:51:10 -0600269 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
270 SET_STD_PCIE_INFO(pci_info[num], 2);
271 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
272 printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
Peter Tyser64917ca2010-01-17 15:38:26 -0600273 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala5e3d7052009-11-04 12:51:10 -0600274 pci_info[num].regs);
275 first_free_busno = fsl_pci_init_port(&pci_info[num++],
276 &pcie2_hose, first_free_busno);
277 } else {
278 printf (" PCIE2: disabled\n");
279 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500280
Kumar Gala5e3d7052009-11-04 12:51:10 -0600281 puts("\n");
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500282#else
Kumar Gala5e3d7052009-11-04 12:51:10 -0600283 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
284#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500285
286#ifdef CONFIG_PCI1
Kumar Gala5e3d7052009-11-04 12:51:10 -0600287 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
288 SET_STD_PCI_INFO(pci_info[num], 1);
289 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500290 printf(" PCI connected to PCI slots as %s" \
Kumar Gala5e3d7052009-11-04 12:51:10 -0600291 " (base address %lx)\n",
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500292 pci_agent ? "Agent" : "Host",
Kumar Gala5e3d7052009-11-04 12:51:10 -0600293 pci_info[num].regs);
294 first_free_busno = fsl_pci_init_port(&pci_info[num++],
295 &pci1_hose, first_free_busno);
296 } else {
297 printf (" PCI: disabled\n");
298 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500299
Kumar Gala5e3d7052009-11-04 12:51:10 -0600300 puts("\n");
301#else
302 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
303#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500304}
305
Jon Loeliger1df170f2008-01-04 12:07:27 -0600306#if defined(CONFIG_OF_BOARD_SETUP)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500307void
308ft_board_setup(void *blob, bd_t *bd)
309{
Peter Tyser8439f052009-09-21 23:09:28 -0500310 ft_cpu_setup(blob, bd);
Jon Loeliger1df170f2008-01-04 12:07:27 -0600311
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500312#ifdef CONFIG_PCI1
Kumar Galac2083e02008-10-22 14:38:55 -0500313 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500314#endif
315#ifdef CONFIG_PCIE1
Kumar Galac2083e02008-10-22 14:38:55 -0500316 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500317#endif
318#ifdef CONFIG_PCIE2
Kumar Galac2083e02008-10-22 14:38:55 -0500319 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500320#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500321}
322#endif
323
324/*
325 * get_board_sys_clk
326 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
327 */
328
329unsigned long
330get_board_sys_clk(ulong dummy)
331{
York Suna8778802007-10-29 13:58:39 -0500332 u8 i;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500333 ulong val = 0;
Kumar Gala048e7ef2009-07-22 10:12:39 -0500334 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500335
Kumar Gala048e7ef2009-07-22 10:12:39 -0500336 i = in_8(pixis_base + PIXIS_SPD);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500337 i &= 0x07;
338
339 switch (i) {
340 case 0:
341 val = 33333000;
342 break;
343 case 1:
344 val = 39999600;
345 break;
346 case 2:
347 val = 49999500;
348 break;
349 case 3:
350 val = 66666000;
351 break;
352 case 4:
353 val = 83332500;
354 break;
355 case 5:
356 val = 99999000;
357 break;
358 case 6:
359 val = 133332000;
360 break;
361 case 7:
362 val = 166665000;
363 break;
364 }
365
366 return val;
367}
Ben Warren65d3d992008-07-11 23:42:19 -0700368
Ben Warren65d3d992008-07-11 23:42:19 -0700369int board_eth_init(bd_t *bis)
370{
Ben Warren89973f82008-08-31 22:22:04 -0700371 return pci_eth_init(bis);
Ben Warren65d3d992008-07-11 23:42:19 -0700372}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600373
374void board_reset(void)
375{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500376 u8 *pixis_base = (u8 *)PIXIS_BASE;
377
378 out_8(pixis_base + PIXIS_RST, 0);
Peter Tyser4ef630d2009-02-05 11:25:25 -0600379
380 while (1)
381 ;
382}