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Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05301/*
York Sunc60dee02014-03-27 17:54:48 -07002 * Copyright 2013-2014 Freescale Semiconductor, Inc.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05303 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * T1040 QDS board configuration file
28 */
29#define CONFIG_T1040QDS
30#define CONFIG_PHYS_64BIT
vijay rai2aea6612014-11-18 12:21:13 +053031#define CONFIG_DISPLAY_BOARDINFO
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053032
33#ifdef CONFIG_RAMBOOT_PBL
34#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090036#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
37#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053038#endif
39
40/* High Level Configuration Options */
41#define CONFIG_BOOKE
42#define CONFIG_E500 /* BOOKE e500 family */
43#define CONFIG_E500MC /* BOOKE e500mc family */
44#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053045#define CONFIG_MP /* support multiple processors */
46
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080047/* support deep sleep */
48#define CONFIG_DEEP_SLEEP
tang yuantian7d0e97a2014-12-18 10:20:07 +080049#if defined(CONFIG_DEEP_SLEEP)
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080050#define CONFIG_SILENT_CONSOLE
tang yuantian7d0e97a2014-12-18 10:20:07 +080051#define CONFIG_BOARD_EARLY_INIT_F
52#endif
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080053
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053054#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053055#define CONFIG_SYS_TEXT_BASE 0xeff40000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053056#endif
57
58#ifndef CONFIG_RESET_VECTOR_ADDRESS
59#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
60#endif
61
62#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
63#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
64#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053065#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053066#define CONFIG_PCI /* Enable PCI/PCIE */
67#define CONFIG_PCI_INDIRECT_BRIDGE
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040068#define CONFIG_PCIE1 /* PCIE controller 1 */
69#define CONFIG_PCIE2 /* PCIE controller 2 */
70#define CONFIG_PCIE3 /* PCIE controller 3 */
71#define CONFIG_PCIE4 /* PCIE controller 4 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053072
73#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
74#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
75
76#define CONFIG_FSL_LAW /* Use common FSL init code */
77
78#define CONFIG_ENV_OVERWRITE
79
80#ifdef CONFIG_SYS_NO_FLASH
81#define CONFIG_ENV_IS_NOWHERE
82#else
83#define CONFIG_FLASH_CFI_DRIVER
84#define CONFIG_SYS_FLASH_CFI
85#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
86#endif
87
88#ifndef CONFIG_SYS_NO_FLASH
89#if defined(CONFIG_SPIFLASH)
90#define CONFIG_SYS_EXTRA_ENV_RELOC
91#define CONFIG_ENV_IS_IN_SPI_FLASH
92#define CONFIG_ENV_SPI_BUS 0
93#define CONFIG_ENV_SPI_CS 0
94#define CONFIG_ENV_SPI_MAX_HZ 10000000
95#define CONFIG_ENV_SPI_MODE 0
96#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
97#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
98#define CONFIG_ENV_SECT_SIZE 0x10000
99#elif defined(CONFIG_SDCARD)
100#define CONFIG_SYS_EXTRA_ENV_RELOC
101#define CONFIG_ENV_IS_IN_MMC
102#define CONFIG_SYS_MMC_ENV_DEV 0
103#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530104#define CONFIG_ENV_OFFSET (512 * 1658)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530105#elif defined(CONFIG_NAND)
106#define CONFIG_SYS_EXTRA_ENV_RELOC
107#define CONFIG_ENV_IS_IN_NAND
108#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530109#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530110#else
111#define CONFIG_ENV_IS_IN_FLASH
112#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
113#define CONFIG_ENV_SIZE 0x2000
114#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
115#endif
116#else /* CONFIG_SYS_NO_FLASH */
117#define CONFIG_ENV_SIZE 0x2000
118#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
119#endif
120
121#ifndef __ASSEMBLY__
122unsigned long get_board_sys_clk(void);
123unsigned long get_board_ddr_clk(void);
124#endif
125
126#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
127#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
128
129/*
130 * These can be toggled for performance analysis, otherwise use default.
131 */
132#define CONFIG_SYS_CACHE_STASHING
133#define CONFIG_BACKSIDE_L2_CACHE
134#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
135#define CONFIG_BTB /* toggle branch predition */
136#define CONFIG_DDR_ECC
137#ifdef CONFIG_DDR_ECC
138#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
139#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
140#endif
141
142#define CONFIG_ENABLE_36BIT_PHYS
143
144#define CONFIG_ADDR_MAP
145#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
146
147#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
148#define CONFIG_SYS_MEMTEST_END 0x00400000
149#define CONFIG_SYS_ALT_MEMTEST
150#define CONFIG_PANIC_HANG /* do not reset board on panic */
151
152/*
153 * Config the L3 Cache as L3 SRAM
154 */
155#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
156
157#define CONFIG_SYS_DCSRBAR 0xf0000000
158#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
159
160/* EEPROM */
161#define CONFIG_ID_EEPROM
162#define CONFIG_SYS_I2C_EEPROM_NXID
163#define CONFIG_SYS_EEPROM_BUS_NUM 0
164#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
165#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
166#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
168
169/*
170 * DDR Setup
171 */
172#define CONFIG_VERY_BIG_RAM
173#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
174#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
175
176/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
177#define CONFIG_DIMM_SLOTS_PER_CTLR 1
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530178#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530179
180#define CONFIG_DDR_SPD
York Sunc60dee02014-03-27 17:54:48 -0700181#ifndef CONFIG_SYS_FSL_DDR4
York Sun5614e712013-09-30 09:22:09 -0700182#define CONFIG_SYS_FSL_DDR3
York Sunc60dee02014-03-27 17:54:48 -0700183#endif
York Sun1b2af9b2014-10-27 11:45:11 -0700184#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530185
186#define CONFIG_SYS_SPD_BUS_NUM 0
187#define SPD_EEPROM_ADDRESS 0x51
188
189#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
190
191/*
192 * IFC Definitions
193 */
194#define CONFIG_SYS_FLASH_BASE 0xe0000000
195#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
196
197#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
198#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
199 + 0x8000000) | \
200 CSPR_PORT_SIZE_16 | \
201 CSPR_MSEL_NOR | \
202 CSPR_V)
203#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
204#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
205 CSPR_PORT_SIZE_16 | \
206 CSPR_MSEL_NOR | \
207 CSPR_V)
208#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530209
210/*
211 * TDM Definition
212 */
213#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
214
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530215/* NOR Flash Timing Params */
216#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
217#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
218 FTIM0_NOR_TEADC(0x5) | \
219 FTIM0_NOR_TEAHC(0x5))
220#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
221 FTIM1_NOR_TRAD_NOR(0x1A) |\
222 FTIM1_NOR_TSEQRAD_NOR(0x13))
223#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
224 FTIM2_NOR_TCH(0x4) | \
225 FTIM2_NOR_TWPH(0x0E) | \
226 FTIM2_NOR_TWP(0x1c))
227#define CONFIG_SYS_NOR_FTIM3 0x0
228
229#define CONFIG_SYS_FLASH_QUIET_TEST
230#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
231
232#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
233#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
234#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
235#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
236
237#define CONFIG_SYS_FLASH_EMPTY_INFO
238#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
239 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
240#define CONFIG_FSL_QIXIS /* use common QIXIS code */
241#define QIXIS_BASE 0xffdf0000
242#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
243#define QIXIS_LBMAP_SWITCH 0x06
244#define QIXIS_LBMAP_MASK 0x0f
245#define QIXIS_LBMAP_SHIFT 0
246#define QIXIS_LBMAP_DFLTBANK 0x00
247#define QIXIS_LBMAP_ALTBANK 0x04
248#define QIXIS_RST_CTL_RESET 0x31
249#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
250#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
251#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Prabhakar Kushwaha8c618dd2013-12-26 12:40:55 +0530252#define QIXIS_RST_FORCE_MEM 0x01
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530253
254#define CONFIG_SYS_CSPR3_EXT (0xf)
255#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
256 | CSPR_PORT_SIZE_8 \
257 | CSPR_MSEL_GPCM \
258 | CSPR_V)
259#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
260#define CONFIG_SYS_CSOR3 0x0
261/* QIXIS Timing parameters for IFC CS3 */
262#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
263 FTIM0_GPCM_TEADC(0x0e) | \
264 FTIM0_GPCM_TEAHC(0x0e))
265#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
266 FTIM1_GPCM_TRAD(0x3f))
267#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Prabhakar Kushwaha562de1d2013-12-12 12:09:01 +0530268 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530269 FTIM2_GPCM_TWP(0x1f))
270#define CONFIG_SYS_CS3_FTIM3 0x0
271
272#define CONFIG_NAND_FSL_IFC
273#define CONFIG_SYS_NAND_BASE 0xff800000
274#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
275
276#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
277#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
278 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
279 | CSPR_MSEL_NAND /* MSEL = NAND */ \
280 | CSPR_V)
281#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
282
283#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
284 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
285 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
286 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
287 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
288 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
289 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
290
291#define CONFIG_SYS_NAND_ONFI_DETECTION
292
293/* ONFI NAND Flash mode0 Timing Params */
294#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
295 FTIM0_NAND_TWP(0x18) | \
296 FTIM0_NAND_TWCHT(0x07) | \
297 FTIM0_NAND_TWH(0x0a))
298#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
299 FTIM1_NAND_TWBE(0x39) | \
300 FTIM1_NAND_TRR(0x0e) | \
301 FTIM1_NAND_TRP(0x18))
302#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
303 FTIM2_NAND_TREH(0x0a) | \
304 FTIM2_NAND_TWHRE(0x1e))
305#define CONFIG_SYS_NAND_FTIM3 0x0
306
307#define CONFIG_SYS_NAND_DDR_LAW 11
308#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
309#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530310#define CONFIG_CMD_NAND
311
312#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
313
314#if defined(CONFIG_NAND)
315#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
316#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
317#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
318#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
319#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
320#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
321#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
322#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
323#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
324#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
325#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
326#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
327#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
328#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
329#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
330#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
331#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
332#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
333#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
334#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
335#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
336#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
337#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
338#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
339#else
340#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
341#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
342#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
343#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
344#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
345#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
346#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
347#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
348#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
349#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
350#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
351#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
352#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
353#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
354#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
355#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
356#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
357#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
358#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
359#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
360#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
361#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
362#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
363#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
364#endif
365
366#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
367
368#if defined(CONFIG_RAMBOOT_PBL)
369#define CONFIG_SYS_RAMBOOT
370#endif
371
372#define CONFIG_BOARD_EARLY_INIT_R
373#define CONFIG_MISC_INIT_R
374
375#define CONFIG_HWCONFIG
376
377/* define to use L1 as initial stack */
378#define CONFIG_L1_INIT_RAM
379#define CONFIG_SYS_INIT_RAM_LOCK
380#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
381#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700382#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530383/* The assembler doesn't like typecast */
384#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
385 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
386 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
387#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
388
389#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
390 GENERATED_GBL_DATA_SIZE)
391#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
392
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530393#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Priyanka Jain337b0c52014-02-26 16:11:53 +0530394#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530395
396/* Serial Port - controlled on board with jumper J8
397 * open - index 2
398 * shorted - index 1
399 */
400#define CONFIG_CONS_INDEX 1
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530401#define CONFIG_SYS_NS16550_SERIAL
402#define CONFIG_SYS_NS16550_REG_SIZE 1
403#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
404
405#define CONFIG_SYS_BAUDRATE_TABLE \
406 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
407
408#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
409#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
410#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
411#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530412#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
413
Priyanka Jain337b0c52014-02-26 16:11:53 +0530414/* Video */
415#define CONFIG_FSL_DIU_FB
416#ifdef CONFIG_FSL_DIU_FB
Wang Dongshengc53711b2014-03-19 10:47:55 +0800417#define CONFIG_FSL_DIU_CH7301
Priyanka Jain337b0c52014-02-26 16:11:53 +0530418#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
419#define CONFIG_VIDEO
420#define CONFIG_CMD_BMP
421#define CONFIG_CFB_CONSOLE
422#define CONFIG_VIDEO_SW_CURSOR
423#define CONFIG_VGA_AS_SINGLE_DEVICE
424#define CONFIG_VIDEO_LOGO
425#define CONFIG_VIDEO_BMP_LOGO
426#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
427/*
428 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
429 * disable empty flash sector detection, which is I/O-intensive.
430 */
431#undef CONFIG_SYS_FLASH_EMPTY_INFO
432#endif
433
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530434/* I2C */
435#define CONFIG_SYS_I2C
436#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530437#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800438#define CONFIG_SYS_FSL_I2C2_SPEED 50000
439#define CONFIG_SYS_FSL_I2C3_SPEED 50000
440#define CONFIG_SYS_FSL_I2C4_SPEED 50000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530441#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530442#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800443#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
444#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530445#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800446#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
447#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
448#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530449
450#define I2C_MUX_PCA_ADDR 0x77
451#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
452
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530453/* I2C bus multiplexer */
454#define I2C_MUX_CH_DEFAULT 0x8
Priyanka Jain337b0c52014-02-26 16:11:53 +0530455#define I2C_MUX_CH_DIU 0xC
456
457/* LDI/DVI Encoder for display */
458#define CONFIG_SYS_I2C_LDI_ADDR 0x38
459#define CONFIG_SYS_I2C_DVI_ADDR 0x75
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530460
461/*
462 * RTC configuration
463 */
464#define RTC
465#define CONFIG_RTC_DS3231 1
466#define CONFIG_SYS_I2C_RTC_ADDR 0x68
467
468/*
469 * eSPI - Enhanced SPI
470 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530471#define CONFIG_SF_DEFAULT_SPEED 10000000
472#define CONFIG_SF_DEFAULT_MODE 0
473
474/*
475 * General PCI
476 * Memory space is mapped 1-1, but I/O space must start from 0.
477 */
478
479#ifdef CONFIG_PCI
480/* controller 1, direct to uli, tgtid 3, Base address 20000 */
481#ifdef CONFIG_PCIE1
482#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
483#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
484#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
485#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
486#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
487#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
488#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
489#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
490#endif
491
492/* controller 2, Slot 2, tgtid 2, Base address 201000 */
493#ifdef CONFIG_PCIE2
494#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
495#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
496#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
497#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
498#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
499#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
500#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
501#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
502#endif
503
504/* controller 3, Slot 1, tgtid 1, Base address 202000 */
505#ifdef CONFIG_PCIE3
506#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
507#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
508#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
509#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
510#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
511#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
512#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
513#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
514#endif
515
516/* controller 4, Base address 203000 */
517#ifdef CONFIG_PCIE4
518#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
519#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
520#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
521#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
522#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
523#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
524#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
525#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
526#endif
527
528#define CONFIG_PCI_PNP /* do pci plug-and-play */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530529
530#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
531#define CONFIG_DOS_PARTITION
532#endif /* CONFIG_PCI */
533
534/* SATA */
535#define CONFIG_FSL_SATA_V2
536#ifdef CONFIG_FSL_SATA_V2
537#define CONFIG_LIBATA
538#define CONFIG_FSL_SATA
539
540#define CONFIG_SYS_SATA_MAX_DEVICE 2
541#define CONFIG_SATA1
542#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
543#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
544#define CONFIG_SATA2
545#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
546#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
547
548#define CONFIG_LBA48
549#define CONFIG_CMD_SATA
550#define CONFIG_DOS_PARTITION
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530551#endif
552
553/*
554* USB
555*/
556#define CONFIG_HAS_FSL_DR_USB
557
558#ifdef CONFIG_HAS_FSL_DR_USB
559#define CONFIG_USB_EHCI
560
561#ifdef CONFIG_USB_EHCI
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530562#define CONFIG_USB_STORAGE
563#define CONFIG_USB_EHCI_FSL
564#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530565#endif
566#endif
567
568#define CONFIG_MMC
569
570#ifdef CONFIG_MMC
571#define CONFIG_FSL_ESDHC
Yangbo Lu12486f32015-09-17 10:27:38 +0800572#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530573#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530574#define CONFIG_GENERIC_MMC
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530575#define CONFIG_DOS_PARTITION
Yangbo Lufa1e0352015-09-17 10:27:27 +0800576#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530577#endif
578
579/* Qman/Bman */
580#ifndef CONFIG_NOBQFMAN
581#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500582#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530583#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
584#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
585#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500586#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
587#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
588#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
589#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
590#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
591 CONFIG_SYS_BMAN_CENA_SIZE)
592#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
593#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500594#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530595#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
596#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
597#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500598#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
599#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
600#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
601#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
602#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
603 CONFIG_SYS_QMAN_CENA_SIZE)
604#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
605#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530606
607#define CONFIG_SYS_DPAA_FMAN
608#define CONFIG_SYS_DPAA_PME
609
Zhao Qiang6259e292014-03-21 16:21:46 +0800610#define CONFIG_QE
611#define CONFIG_U_QE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530612/* Default address of microcode for the Linux Fman driver */
613#if defined(CONFIG_SPIFLASH)
614/*
615 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
616 * env, so we got 0x110000.
617 */
618#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800619#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530620#elif defined(CONFIG_SDCARD)
621/*
622 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530623 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
624 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530625 */
626#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800627#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530628#elif defined(CONFIG_NAND)
629#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800630#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530631#else
632#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800633#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Zhao Qiang6259e292014-03-21 16:21:46 +0800634#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530635#endif
636#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
637#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
638#endif /* CONFIG_NOBQFMAN */
639
640#ifdef CONFIG_SYS_DPAA_FMAN
641#define CONFIG_FMAN_ENET
642#define CONFIG_PHYLIB_10G
643#define CONFIG_PHY_VITESSE
644#define CONFIG_PHY_REALTEK
645#define CONFIG_PHY_TERANETICS
646#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
647#define SGMII_CARD_PORT2_PHY_ADDR 0x10
648#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
649#define SGMII_CARD_PORT4_PHY_ADDR 0x11
650#endif
651
652#ifdef CONFIG_FMAN_ENET
Prabhakar Kushwaha5b7672f2014-01-27 15:55:20 +0530653#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
654#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530655
656#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
657#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
658#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
659#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
660
661#define CONFIG_MII /* MII PHY management */
662#define CONFIG_ETHPRIME "FM1@DTSEC1"
663#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
664#endif
665
Codrin Ciubotariua83fccc2015-01-21 11:54:11 +0200666/* Enable VSC9953 L2 Switch driver */
667#define CONFIG_VSC9953
Codrin Ciubotariu4c1ceb62016-03-14 13:46:51 +0200668#define CONFIG_CMD_ETHSW
Codrin Ciubotariua83fccc2015-01-21 11:54:11 +0200669#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
670#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
671
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530672/*
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530673 * Dynamic MTD Partition support with mtdparts
674 */
675#ifndef CONFIG_SYS_NO_FLASH
676#define CONFIG_MTD_DEVICE
677#define CONFIG_MTD_PARTITIONS
678#define CONFIG_CMD_MTDPARTS
679#define CONFIG_FLASH_CFI_MTD
680#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
681 "spi0=spife110000.0"
682#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
683 "128k(dtb),96m(fs),-(user);"\
684 "fff800000.flash:2m(uboot),9m(kernel),"\
685 "128k(dtb),96m(fs),-(user);spife110000.0:" \
686 "2m(uboot),9m(kernel),128k(dtb),-(user)"
687#endif
688
689/*
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530690 * Environment
691 */
692#define CONFIG_LOADS_ECHO /* echo on for serial download */
693#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
694
695/*
696 * Command line configuration.
697 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530698#define CONFIG_CMD_DATE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530699#define CONFIG_CMD_EEPROM
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530700#define CONFIG_CMD_ERRATA
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530701#define CONFIG_CMD_IRQ
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530702#define CONFIG_CMD_REGINFO
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530703
704#ifdef CONFIG_PCI
705#define CONFIG_CMD_PCI
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530706#endif
707
Ruchika Gupta737537e2014-10-15 11:35:31 +0530708/* Hash command with SHA acceleration supported in hardware */
709#ifdef CONFIG_FSL_CAAM
710#define CONFIG_CMD_HASH
711#define CONFIG_SHA_HW_ACCEL
712#endif
713
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530714/*
715 * Miscellaneous configurable options
716 */
717#define CONFIG_SYS_LONGHELP /* undef to save memory */
718#define CONFIG_CMDLINE_EDITING /* Command-line editing */
719#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
720#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530721#ifdef CONFIG_CMD_KGDB
722#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
723#else
724#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
725#endif
726#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
727#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
728#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530729
730/*
731 * For booting Linux, the board info and command line data
732 * have to be in the first 64 MB of memory, since this is
733 * the maximum mapped by the Linux kernel during initialization.
734 */
735#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
736#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
737
738#ifdef CONFIG_CMD_KGDB
739#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530740#endif
741
742/*
743 * Environment Configuration
744 */
745#define CONFIG_ROOTPATH "/opt/nfsroot"
746#define CONFIG_BOOTFILE "uImage"
747#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
748
749/* default location for tftp and bootm */
750#define CONFIG_LOADADDR 1000000
751
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530752
753#define CONFIG_BAUDRATE 115200
754
755#define __USB_PHY_TYPE utmi
756
757#define CONFIG_EXTRA_ENV_SETTINGS \
York Sun1b2af9b2014-10-27 11:45:11 -0700758 "hwconfig=fsl_ddr:bank_intlv=auto;" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530759 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
760 "netdev=eth0\0" \
Priyanka Jain337b0c52014-02-26 16:11:53 +0530761 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530762 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
763 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
764 "tftpflash=tftpboot $loadaddr $uboot && " \
765 "protect off $ubootaddr +$filesize && " \
766 "erase $ubootaddr +$filesize && " \
767 "cp.b $loadaddr $ubootaddr $filesize && " \
768 "protect on $ubootaddr +$filesize && " \
769 "cmp.b $loadaddr $ubootaddr $filesize\0" \
770 "consoledev=ttyS0\0" \
771 "ramdiskaddr=2000000\0" \
772 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
773 "fdtaddr=c00000\0" \
774 "fdtfile=t1040qds/t1040qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500775 "bdev=sda3\0"
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530776
777#define CONFIG_LINUX \
778 "setenv bootargs root=/dev/ram rw " \
779 "console=$consoledev,$baudrate $othbootargs;" \
780 "setenv ramdiskaddr 0x02000000;" \
781 "setenv fdtaddr 0x00c00000;" \
782 "setenv loadaddr 0x1000000;" \
783 "bootm $loadaddr $ramdiskaddr $fdtaddr"
784
785#define CONFIG_HDBOOT \
786 "setenv bootargs root=/dev/$bdev rw " \
787 "console=$consoledev,$baudrate $othbootargs;" \
788 "tftp $loadaddr $bootfile;" \
789 "tftp $fdtaddr $fdtfile;" \
790 "bootm $loadaddr - $fdtaddr"
791
792#define CONFIG_NFSBOOTCOMMAND \
793 "setenv bootargs root=/dev/nfs rw " \
794 "nfsroot=$serverip:$rootpath " \
795 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
796 "console=$consoledev,$baudrate $othbootargs;" \
797 "tftp $loadaddr $bootfile;" \
798 "tftp $fdtaddr $fdtfile;" \
799 "bootm $loadaddr - $fdtaddr"
800
801#define CONFIG_RAMBOOTCOMMAND \
802 "setenv bootargs root=/dev/ram rw " \
803 "console=$consoledev,$baudrate $othbootargs;" \
804 "tftp $ramdiskaddr $ramdiskfile;" \
805 "tftp $loadaddr $bootfile;" \
806 "tftp $fdtaddr $fdtfile;" \
807 "bootm $loadaddr $ramdiskaddr $fdtaddr"
808
809#define CONFIG_BOOTCOMMAND CONFIG_LINUX
810
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530811#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530812
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530813#endif /* __CONFIG_H */