Bin Meng | b2e02d2 | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 9 | #include <asm/irq.h> |
Bin Meng | adfe3b2 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 10 | #include <asm/pci.h> |
Bin Meng | b2e02d2 | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 11 | #include <asm/post.h> |
Bin Meng | afbf140 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 12 | #include <asm/arch/device.h> |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 13 | #include <asm/arch/tnc.h> |
Simon Glass | 1021af4 | 2015-01-27 22:13:36 -0700 | [diff] [blame] | 14 | #include <asm/fsp/fsp_support.h> |
Bin Meng | b2e02d2 | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 15 | #include <asm/processor.h> |
| 16 | |
Bin Meng | adfe3b2 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 17 | static void unprotect_spi_flash(void) |
| 18 | { |
| 19 | u32 bc; |
| 20 | |
Bin Meng | 9704f23 | 2015-04-13 19:03:42 +0800 | [diff] [blame] | 21 | bc = x86_pci_read_config32(TNC_LPC, 0xd8); |
Bin Meng | adfe3b2 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 22 | bc |= 0x1; /* unprotect the flash */ |
Bin Meng | 9704f23 | 2015-04-13 19:03:42 +0800 | [diff] [blame] | 23 | x86_pci_write_config32(TNC_LPC, 0xd8, bc); |
Bin Meng | adfe3b2 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 24 | } |
| 25 | |
Bin Meng | 1f124eb | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 26 | static void __maybe_unused disable_igd(void) |
| 27 | { |
| 28 | u32 gc; |
| 29 | |
| 30 | gc = x86_pci_read_config32(TNC_IGD, IGD_GC); |
| 31 | gc &= ~GMS_MASK; |
| 32 | gc |= VGA_DISABLE; |
| 33 | x86_pci_write_config32(TNC_IGD, IGD_GC, gc); |
| 34 | } |
| 35 | |
Bin Meng | b2e02d2 | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 36 | int arch_cpu_init(void) |
| 37 | { |
Bin Meng | adfe3b2 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 38 | int ret; |
| 39 | |
Bin Meng | b2e02d2 | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 40 | post_code(POST_CPU_INIT); |
| 41 | #ifdef CONFIG_SYS_X86_TSC_TIMER |
| 42 | timer_set_base(rdtsc()); |
| 43 | #endif |
| 44 | |
Bin Meng | adfe3b2 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 45 | ret = x86_cpu_init_f(); |
| 46 | if (ret) |
| 47 | return ret; |
| 48 | |
Bin Meng | adfe3b2 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 49 | return 0; |
Bin Meng | b2e02d2 | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 50 | } |
Bin Meng | afbf140 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 51 | |
Bin Meng | 1f124eb | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 52 | int arch_early_init_r(void) |
| 53 | { |
| 54 | #ifdef CONFIG_DISABLE_IGD |
| 55 | disable_igd(); |
| 56 | #endif |
| 57 | |
| 58 | return 0; |
| 59 | } |
| 60 | |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 61 | void cpu_irq_init(void) |
| 62 | { |
| 63 | struct tnc_rcba *rcba; |
| 64 | u32 base; |
| 65 | |
| 66 | base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); |
| 67 | base &= ~MEM_BAR_EN; |
| 68 | rcba = (struct tnc_rcba *)base; |
| 69 | |
| 70 | /* Make sure all internal PCI devices are using INTA */ |
| 71 | writel(INTA, &rcba->d02ip); |
| 72 | writel(INTA, &rcba->d03ip); |
| 73 | writel(INTA, &rcba->d27ip); |
| 74 | writel(INTA, &rcba->d31ip); |
| 75 | writel(INTA, &rcba->d23ip); |
| 76 | writel(INTA, &rcba->d24ip); |
| 77 | writel(INTA, &rcba->d25ip); |
| 78 | writel(INTA, &rcba->d26ip); |
| 79 | |
| 80 | /* |
| 81 | * Route TunnelCreek PCI device interrupt pin to PIRQ |
| 82 | * |
| 83 | * Since PCIe downstream ports received INTx are routed to PIRQ |
Bin Meng | cdb6bab | 2015-06-23 12:18:55 +0800 | [diff] [blame] | 84 | * A/B/C/D directly and not configurable, we have to route PCIe |
| 85 | * root ports' INTx to PIRQ A/B/C/D as well. For other devices |
| 86 | * on TunneCreek, route them to PIRQ E/F/G/H. |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 87 | */ |
| 88 | writew(PIRQE, &rcba->d02ir); |
| 89 | writew(PIRQF, &rcba->d03ir); |
| 90 | writew(PIRQG, &rcba->d27ir); |
| 91 | writew(PIRQH, &rcba->d31ir); |
Bin Meng | cdb6bab | 2015-06-23 12:18:55 +0800 | [diff] [blame] | 92 | writew(PIRQA, &rcba->d23ir); |
| 93 | writew(PIRQB, &rcba->d24ir); |
| 94 | writew(PIRQC, &rcba->d25ir); |
| 95 | writew(PIRQD, &rcba->d26ir); |
Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 96 | } |
| 97 | |
Bin Meng | afbf140 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 98 | int arch_misc_init(void) |
| 99 | { |
Bin Meng | 090290f | 2015-08-20 06:40:21 -0700 | [diff] [blame] | 100 | unprotect_spi_flash(); |
| 101 | |
Simon Glass | 7e4be12 | 2015-08-10 07:05:08 -0600 | [diff] [blame] | 102 | return pirq_init(); |
Bin Meng | afbf140 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 103 | } |