blob: 0c02a44f63f673ce3475019f7a6508d3ce475288 [file] [log] [blame]
Bin Mengb2e02d22014-12-17 15:50:36 +08001/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
Bin Meng9c7dea62015-05-25 22:35:04 +08009#include <asm/irq.h>
Bin Mengadfe3b22014-12-17 15:50:44 +080010#include <asm/pci.h>
Bin Mengb2e02d22014-12-17 15:50:36 +080011#include <asm/post.h>
Bin Mengafbf1402015-04-24 18:10:06 +080012#include <asm/arch/device.h>
Bin Meng9c7dea62015-05-25 22:35:04 +080013#include <asm/arch/tnc.h>
Simon Glass1021af42015-01-27 22:13:36 -070014#include <asm/fsp/fsp_support.h>
Bin Mengb2e02d22014-12-17 15:50:36 +080015#include <asm/processor.h>
16
Bin Mengadfe3b22014-12-17 15:50:44 +080017static void unprotect_spi_flash(void)
18{
19 u32 bc;
20
Bin Meng9704f232015-04-13 19:03:42 +080021 bc = x86_pci_read_config32(TNC_LPC, 0xd8);
Bin Mengadfe3b22014-12-17 15:50:44 +080022 bc |= 0x1; /* unprotect the flash */
Bin Meng9704f232015-04-13 19:03:42 +080023 x86_pci_write_config32(TNC_LPC, 0xd8, bc);
Bin Mengadfe3b22014-12-17 15:50:44 +080024}
25
Bin Meng1f124eb2015-10-01 00:36:04 -070026static void __maybe_unused disable_igd(void)
27{
28 u32 gc;
29
30 gc = x86_pci_read_config32(TNC_IGD, IGD_GC);
31 gc &= ~GMS_MASK;
32 gc |= VGA_DISABLE;
33 x86_pci_write_config32(TNC_IGD, IGD_GC, gc);
34}
35
Bin Mengb2e02d22014-12-17 15:50:36 +080036int arch_cpu_init(void)
37{
Bin Mengadfe3b22014-12-17 15:50:44 +080038 int ret;
39
Bin Mengb2e02d22014-12-17 15:50:36 +080040 post_code(POST_CPU_INIT);
41#ifdef CONFIG_SYS_X86_TSC_TIMER
42 timer_set_base(rdtsc());
43#endif
44
Bin Mengadfe3b22014-12-17 15:50:44 +080045 ret = x86_cpu_init_f();
46 if (ret)
47 return ret;
48
Bin Mengadfe3b22014-12-17 15:50:44 +080049 return 0;
Bin Mengb2e02d22014-12-17 15:50:36 +080050}
Bin Mengafbf1402015-04-24 18:10:06 +080051
Bin Meng1f124eb2015-10-01 00:36:04 -070052int arch_early_init_r(void)
53{
54#ifdef CONFIG_DISABLE_IGD
55 disable_igd();
56#endif
57
58 return 0;
59}
60
Bin Meng9c7dea62015-05-25 22:35:04 +080061void cpu_irq_init(void)
62{
63 struct tnc_rcba *rcba;
64 u32 base;
65
66 base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
67 base &= ~MEM_BAR_EN;
68 rcba = (struct tnc_rcba *)base;
69
70 /* Make sure all internal PCI devices are using INTA */
71 writel(INTA, &rcba->d02ip);
72 writel(INTA, &rcba->d03ip);
73 writel(INTA, &rcba->d27ip);
74 writel(INTA, &rcba->d31ip);
75 writel(INTA, &rcba->d23ip);
76 writel(INTA, &rcba->d24ip);
77 writel(INTA, &rcba->d25ip);
78 writel(INTA, &rcba->d26ip);
79
80 /*
81 * Route TunnelCreek PCI device interrupt pin to PIRQ
82 *
83 * Since PCIe downstream ports received INTx are routed to PIRQ
Bin Mengcdb6bab2015-06-23 12:18:55 +080084 * A/B/C/D directly and not configurable, we have to route PCIe
85 * root ports' INTx to PIRQ A/B/C/D as well. For other devices
86 * on TunneCreek, route them to PIRQ E/F/G/H.
Bin Meng9c7dea62015-05-25 22:35:04 +080087 */
88 writew(PIRQE, &rcba->d02ir);
89 writew(PIRQF, &rcba->d03ir);
90 writew(PIRQG, &rcba->d27ir);
91 writew(PIRQH, &rcba->d31ir);
Bin Mengcdb6bab2015-06-23 12:18:55 +080092 writew(PIRQA, &rcba->d23ir);
93 writew(PIRQB, &rcba->d24ir);
94 writew(PIRQC, &rcba->d25ir);
95 writew(PIRQD, &rcba->d26ir);
Bin Meng9c7dea62015-05-25 22:35:04 +080096}
97
Bin Mengafbf1402015-04-24 18:10:06 +080098int arch_misc_init(void)
99{
Bin Meng090290f2015-08-20 06:40:21 -0700100 unprotect_spi_flash();
101
Simon Glass7e4be122015-08-10 07:05:08 -0600102 return pirq_init();
Bin Mengafbf1402015-04-24 18:10:06 +0800103}