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Mingkai Hu4f1d1b72011-07-07 12:29:15 +08001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08005 */
6
7/*
8 * P2041 RDB board configuration file
Scott Wood3e978f52012-08-14 10:14:51 +00009 * Also supports P2040 RDB
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_P2041RDB
15#define CONFIG_PHYS_64BIT
16#define CONFIG_PPC_P2041
17
18#ifdef CONFIG_RAMBOOT_PBL
19#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Valentin Longchampb38181f2013-01-04 04:06:17 +000021#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
22#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080023#endif
24
Liu Gang461632b2012-08-09 05:10:03 +000025#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
Liu Gangff65f122012-08-09 05:09:59 +000026/* Set 1M boot space */
Liu Gang461632b2012-08-09 05:10:03 +000027#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
28#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
29 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
Liu Gangff65f122012-08-09 05:09:59 +000030#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31#define CONFIG_SYS_NO_FLASH
32#endif
33
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080034/* High Level Configuration Options */
35#define CONFIG_BOOKE
36#define CONFIG_E500 /* BOOKE e500 family */
37#define CONFIG_E500MC /* BOOKE e500mc family */
38#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
39#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
40#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
41#define CONFIG_MP /* support multiple processors */
42
43#ifndef CONFIG_SYS_TEXT_BASE
44#define CONFIG_SYS_TEXT_BASE 0xeff80000
45#endif
46
47#ifndef CONFIG_RESET_VECTOR_ADDRESS
48#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
49#endif
50
51#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
52#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
53#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
54#define CONFIG_PCI /* Enable PCI/PCIE */
55#define CONFIG_PCIE1 /* PCIE controler 1 */
56#define CONFIG_PCIE2 /* PCIE controler 2 */
57#define CONFIG_PCIE3 /* PCIE controler 3 */
58#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
59#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
60
61#define CONFIG_SYS_SRIO
62#define CONFIG_SRIO1 /* SRIO port 1 */
63#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gangc8b28152013-05-07 16:30:46 +080064#define CONFIG_SRIO_PCIE_BOOT_MASTER
Kumar Gala4d28db82011-10-14 13:28:52 -050065#define CONFIG_SYS_DPAA_RMAN /* RMan */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080066
67#define CONFIG_FSL_LAW /* Use common FSL init code */
68
69#define CONFIG_ENV_OVERWRITE
70
71#ifdef CONFIG_SYS_NO_FLASH
Liu Gang461632b2012-08-09 05:10:03 +000072#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080073#define CONFIG_ENV_IS_NOWHERE
Shaohui Xie0f57f6a2012-06-28 23:35:34 +000074#endif
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080075#else
76#define CONFIG_FLASH_CFI_DRIVER
77#define CONFIG_SYS_FLASH_CFI
Shaohui Xie0f57f6a2012-06-28 23:35:34 +000078#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080079#endif
80
81#if defined(CONFIG_SPIFLASH)
82 #define CONFIG_SYS_EXTRA_ENV_RELOC
83 #define CONFIG_ENV_IS_IN_SPI_FLASH
84 #define CONFIG_ENV_SPI_BUS 0
85 #define CONFIG_ENV_SPI_CS 0
86 #define CONFIG_ENV_SPI_MAX_HZ 10000000
87 #define CONFIG_ENV_SPI_MODE 0
88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
90 #define CONFIG_ENV_SECT_SIZE 0x10000
91#elif defined(CONFIG_SDCARD)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +000094 #define CONFIG_FSL_FIXED_MMC_LOCATION
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080095 #define CONFIG_SYS_MMC_ENV_DEV 0
96 #define CONFIG_ENV_SIZE 0x2000
97 #define CONFIG_ENV_OFFSET (512 * 1097)
Shaohui Xie15c8c6c2012-02-28 23:28:40 +000098#elif defined(CONFIG_NAND)
99#define CONFIG_SYS_EXTRA_ENV_RELOC
100#define CONFIG_ENV_IS_IN_NAND
101#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
102#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang461632b2012-08-09 05:10:03 +0000103#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gangff65f122012-08-09 05:09:59 +0000104#define CONFIG_ENV_IS_IN_REMOTE
105#define CONFIG_ENV_ADDR 0xffe20000
106#define CONFIG_ENV_SIZE 0x2000
Shaohui Xie0f57f6a2012-06-28 23:35:34 +0000107#elif defined(CONFIG_ENV_IS_NOWHERE)
Liu Gangff65f122012-08-09 05:09:59 +0000108#define CONFIG_ENV_SIZE 0x2000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800109#else
110 #define CONFIG_ENV_IS_IN_FLASH
111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
112 - CONFIG_ENV_SECT_SIZE)
113 #define CONFIG_ENV_SIZE 0x2000
114 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
115#endif
116
Shaohui Xie44d50f02011-09-13 17:55:11 +0800117#ifndef __ASSEMBLY__
118unsigned long get_board_sys_clk(unsigned long dummy);
119#endif
120#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800121
122/*
123 * These can be toggled for performance analysis, otherwise use default.
124 */
125#define CONFIG_SYS_CACHE_STASHING
Mingkai Hucd420e02011-07-21 17:03:54 -0500126#define CONFIG_BACKSIDE_L2_CACHE
127#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800128#define CONFIG_BTB /* toggle branch predition */
129
130#define CONFIG_ENABLE_36BIT_PHYS
131
132#ifdef CONFIG_PHYS_64BIT
133#define CONFIG_ADDR_MAP
134#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
135#endif
136
137#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
138#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x00400000
140#define CONFIG_SYS_ALT_MEMTEST
141#define CONFIG_PANIC_HANG /* do not reset board on panic */
142
143/*
144 * Config the L3 Cache as L3 SRAM
145 */
146#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
147#ifdef CONFIG_PHYS_64BIT
148#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
149 CONFIG_RAMBOOT_TEXT_BASE)
150#else
151#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
152#endif
153#define CONFIG_SYS_L3_SIZE (1024 << 10)
154#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
155
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800156#ifdef CONFIG_PHYS_64BIT
157#define CONFIG_SYS_DCSRBAR 0xf0000000
158#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
159#endif
160
161/* EEPROM */
162#define CONFIG_ID_EEPROM
163#define CONFIG_SYS_I2C_EEPROM_NXID
164#define CONFIG_SYS_EEPROM_BUS_NUM 0
165#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
166#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167
168/*
169 * DDR Setup
170 */
171#define CONFIG_VERY_BIG_RAM
172#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
173#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
174
175#define CONFIG_DIMM_SLOTS_PER_CTLR 1
176#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
177
178#define CONFIG_DDR_SPD
179#define CONFIG_FSL_DDR3
180
181#define CONFIG_SYS_SPD_BUS_NUM 0
182#define SPD_EEPROM_ADDRESS 0x52
183#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
184
185/*
186 * Local Bus Definitions
187 */
188
189/* Set the local bus clock 1/8 of platform clock */
190#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
191
York Sunca1b0b82012-10-26 16:40:15 +0000192/*
193 * This board doesn't have a promjet connector.
194 * However, it uses commone corenet board LAW and TLB.
195 * It is necessary to use the same start address with proper offset.
196 */
197#define CONFIG_SYS_FLASH_BASE 0xe0000000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800198#ifdef CONFIG_PHYS_64BIT
York Sunca1b0b82012-10-26 16:40:15 +0000199#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800200#else
201#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
202#endif
203
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000204#define CONFIG_SYS_FLASH_BR_PRELIM \
York Sunca1b0b82012-10-26 16:40:15 +0000205 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
206 BR_PS_16 | BR_V)
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000207#define CONFIG_SYS_FLASH_OR_PRELIM \
208 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
209 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800210
211#define CONFIG_FSL_CPLD
212#define CPLD_BASE 0xffdf0000 /* CPLD registers */
213#ifdef CONFIG_PHYS_64BIT
214#define CPLD_BASE_PHYS 0xfffdf0000ull
215#else
216#define CPLD_BASE_PHYS CPLD_BASE
217#endif
218
219#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
220#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
221
222#define PIXIS_LBMAP_SWITCH 7
223#define PIXIS_LBMAP_MASK 0xf0
224#define PIXIS_LBMAP_SHIFT 4
225#define PIXIS_LBMAP_ALTBANK 0x40
226
227#define CONFIG_SYS_FLASH_QUIET_TEST
228#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
229
230#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
231#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
232#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
233#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
234
235#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
236
237#if defined(CONFIG_RAMBOOT_PBL)
238#define CONFIG_SYS_RAMBOOT
239#endif
240
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000241#define CONFIG_NAND_FSL_ELBC
242/* Nand Flash */
243#ifdef CONFIG_NAND_FSL_ELBC
244#define CONFIG_SYS_NAND_BASE 0xffa00000
245#ifdef CONFIG_PHYS_64BIT
246#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
247#else
248#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
249#endif
250
251#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
252#define CONFIG_SYS_MAX_NAND_DEVICE 1
253#define CONFIG_MTD_NAND_VERIFY_WRITE
254#define CONFIG_CMD_NAND
255#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
256
257/* NAND flash config */
258#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
260 | BR_PS_8 /* Port Size = 8 bit */ \
261 | BR_MS_FCM /* MSEL = FCM */ \
262 | BR_V) /* valid */
263#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
264 | OR_FCM_PGS /* Large Page*/ \
265 | OR_FCM_CSCT \
266 | OR_FCM_CST \
267 | OR_FCM_CHT \
268 | OR_FCM_SCY_1 \
269 | OR_FCM_TRLX \
270 | OR_FCM_EHTR)
271
272#ifdef CONFIG_NAND
273#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
274#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
275#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
276#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
277#else
278#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
279#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
280#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
281#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
282#endif
283#else
284#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
285#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
286#endif /* CONFIG_NAND_FSL_ELBC */
287
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800288#define CONFIG_SYS_FLASH_EMPTY_INFO
289#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
York Sunca1b0b82012-10-26 16:40:15 +0000290#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800291
292#define CONFIG_BOARD_EARLY_INIT_F
293#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
294#define CONFIG_MISC_INIT_R
295
296#define CONFIG_HWCONFIG
297
298/* define to use L1 as initial stack */
299#define CONFIG_L1_INIT_RAM
300#define CONFIG_SYS_INIT_RAM_LOCK
301#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
302#ifdef CONFIG_PHYS_64BIT
303#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
304#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
305/* The assembler doesn't like typecast */
306#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
307 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
308 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
309#else
310#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
311#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
312#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
313#endif
314#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
315
316#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
317 GENERATED_GBL_DATA_SIZE)
318#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
319
320#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
321#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
322
323/* Serial Port - controlled on board with jumper J8
324 * open - index 2
325 * shorted - index 1
326 */
327#define CONFIG_CONS_INDEX 1
328#define CONFIG_SYS_NS16550
329#define CONFIG_SYS_NS16550_SERIAL
330#define CONFIG_SYS_NS16550_REG_SIZE 1
331#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
332
333#define CONFIG_SYS_BAUDRATE_TABLE \
334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
335
336#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
337#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
338#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
339#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
340
341/* Use the HUSH parser */
342#define CONFIG_SYS_HUSH_PARSER
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800343
344/* pass open firmware flat tree */
345#define CONFIG_OF_LIBFDT
346#define CONFIG_OF_BOARD_SETUP
347#define CONFIG_OF_STDOUT_VIA_ALIAS
348
349/* new uImage format support */
350#define CONFIG_FIT
351#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
352
353/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200354#define CONFIG_SYS_I2C
355#define CONFIG_SYS_I2C_FSL
356#define CONFIG_SYS_FSL_I2C_SPEED 400000
357#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
358#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
359#define CONFIG_SYS_FSL_I2C2_SPEED 400000
360#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
361#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800362
363/*
364 * RapidIO
365 */
366#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
367#ifdef CONFIG_PHYS_64BIT
368#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
369#else
370#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
371#endif
372#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
373
374#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
375#ifdef CONFIG_PHYS_64BIT
376#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
377#else
378#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
379#endif
380#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
381
382/*
Liu Gangff65f122012-08-09 05:09:59 +0000383 * for slave u-boot IMAGE instored in master memory space,
384 * PHYS must be aligned based on the SIZE
385 */
Liu Gangb5f7c872012-08-09 05:10:02 +0000386#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
387#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
388#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
389#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
Liu Gangff65f122012-08-09 05:09:59 +0000390/*
391 * for slave UCODE and ENV instored in master memory space,
392 * PHYS must be aligned based on the SIZE
393 */
Liu Gangb5f7c872012-08-09 05:10:02 +0000394#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
395#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
396#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
Liu Gangff65f122012-08-09 05:09:59 +0000397
398/* slave core release by master*/
Liu Gangb5f7c872012-08-09 05:10:02 +0000399#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
400#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
Liu Gangff65f122012-08-09 05:09:59 +0000401
402/*
Liu Gang461632b2012-08-09 05:10:03 +0000403 * SRIO_PCIE_BOOT - SLAVE
Liu Gangff65f122012-08-09 05:09:59 +0000404 */
Liu Gang461632b2012-08-09 05:10:03 +0000405#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
406#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
407#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
408 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
Liu Gangff65f122012-08-09 05:09:59 +0000409#endif
410
411/*
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800412 * eSPI - Enhanced SPI
413 */
414#define CONFIG_FSL_ESPI
415#define CONFIG_SPI_FLASH
416#define CONFIG_SPI_FLASH_SPANSION
417#define CONFIG_CMD_SF
418#define CONFIG_SF_DEFAULT_SPEED 10000000
419#define CONFIG_SF_DEFAULT_MODE 0
420
421/*
422 * General PCI
423 * Memory space is mapped 1-1, but I/O space must start from 0.
424 */
425
426/* controller 1, direct to uli, tgtid 3, Base address 20000 */
427#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
428#ifdef CONFIG_PHYS_64BIT
429#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
430#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
431#else
432#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
433#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
434#endif
435#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
436#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
437#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
438#ifdef CONFIG_PHYS_64BIT
439#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
440#else
441#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
442#endif
443#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
444
445/* controller 2, Slot 2, tgtid 2, Base address 201000 */
446#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
447#ifdef CONFIG_PHYS_64BIT
448#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
449#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
450#else
451#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
452#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
453#endif
454#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
455#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
456#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
457#ifdef CONFIG_PHYS_64BIT
458#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
459#else
460#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
461#endif
462#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
463
464/* controller 3, Slot 1, tgtid 1, Base address 202000 */
465#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
466#ifdef CONFIG_PHYS_64BIT
467#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
468#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
469#else
470#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
471#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
472#endif
473#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
474#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
475#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
478#else
479#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
480#endif
481#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
482
483/* Qman/Bman */
484#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
485#define CONFIG_SYS_BMAN_NUM_PORTALS 10
486#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
487#ifdef CONFIG_PHYS_64BIT
488#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
489#else
490#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
491#endif
492#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
493#define CONFIG_SYS_QMAN_NUM_PORTALS 10
494#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
495#ifdef CONFIG_PHYS_64BIT
496#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
497#else
498#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
499#endif
500#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
501
502#define CONFIG_SYS_DPAA_FMAN
503#define CONFIG_SYS_DPAA_PME
504/* Default address of microcode for the Linux Fman driver */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800505#if defined(CONFIG_SPIFLASH)
506/*
507 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
508 * env, so we got 0x110000.
509 */
Timur Tabif2717b42011-11-22 09:21:25 -0600510#define CONFIG_SYS_QE_FW_IN_SPIFLASH
511#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800512#elif defined(CONFIG_SDCARD)
513/*
514 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
515 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
516 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
517 */
Timur Tabif2717b42011-11-22 09:21:25 -0600518#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
519#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800520#elif defined(CONFIG_NAND)
Timur Tabif2717b42011-11-22 09:21:25 -0600521#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
522#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang461632b2012-08-09 05:10:03 +0000523#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gangff65f122012-08-09 05:09:59 +0000524/*
525 * Slave has no ucode locally, it can fetch this from remote. When implementing
526 * in two corenet boards, slave's ucode could be stored in master's memory
527 * space, the address can be mapped from slave TLB->slave LAW->
Liu Gang461632b2012-08-09 05:10:03 +0000528 * slave SRIO or PCIE outbound window->master inbound window->
529 * master LAW->the ucode address in master's memory space.
Liu Gangff65f122012-08-09 05:09:59 +0000530 */
531#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
532#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800533#else
Timur Tabif2717b42011-11-22 09:21:25 -0600534#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
York Sun021382c2012-10-19 08:35:12 +0000535#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800536#endif
Timur Tabif2717b42011-11-22 09:21:25 -0600537#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
538#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800539
540#ifdef CONFIG_SYS_DPAA_FMAN
541#define CONFIG_FMAN_ENET
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800542#define CONFIG_PHYLIB_10G
543#define CONFIG_PHY_VITESSE
544#define CONFIG_PHY_TERANETICS
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800545#endif
546
547#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000548#define CONFIG_PCI_INDIRECT_BRIDGE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800549#define CONFIG_PCI_PNP /* do pci plug-and-play */
550#define CONFIG_E1000
551
552#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
553#define CONFIG_DOS_PARTITION
554#endif /* CONFIG_PCI */
555
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800556/* SATA */
Zang Roy-R619119760b272012-11-26 00:05:38 +0000557#define CONFIG_FSL_SATA_V2
558
559#ifdef CONFIG_FSL_SATA_V2
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800560#define CONFIG_FSL_SATA
Timur Tabi3e0529f2011-11-21 17:10:22 -0600561#define CONFIG_LIBATA
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800562
563#define CONFIG_SYS_SATA_MAX_DEVICE 2
564#define CONFIG_SATA1
565#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
566#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
567#define CONFIG_SATA2
568#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
569#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
570
571#define CONFIG_LBA48
572#define CONFIG_CMD_SATA
573#define CONFIG_DOS_PARTITION
574#define CONFIG_CMD_EXT2
575#endif
576
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800577#ifdef CONFIG_FMAN_ENET
578#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
579#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
580#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
581#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
582#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
583
584#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
585#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
586#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
587#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
588
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800589#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
590
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800591#define CONFIG_SYS_TBIPA_VALUE 8
592#define CONFIG_MII /* MII PHY management */
593#define CONFIG_ETHPRIME "FM1@DTSEC1"
594#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
595#endif
596
597/*
598 * Environment
599 */
600#define CONFIG_LOADS_ECHO /* echo on for serial download */
601#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
602
603/*
604 * Command line configuration.
605 */
606#include <config_cmd_default.h>
607
608#define CONFIG_CMD_DHCP
609#define CONFIG_CMD_ELF
610#define CONFIG_CMD_ERRATA
611#define CONFIG_CMD_GREPENV
612#define CONFIG_CMD_IRQ
613#define CONFIG_CMD_I2C
614#define CONFIG_CMD_MII
615#define CONFIG_CMD_PING
616#define CONFIG_CMD_SETEXPR
617
618#ifdef CONFIG_PCI
619#define CONFIG_CMD_PCI
620#define CONFIG_CMD_NET
621#endif
622
623/*
624* USB
625*/
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000626#define CONFIG_HAS_FSL_DR_USB
627#define CONFIG_HAS_FSL_MPH_USB
628
629#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800630#define CONFIG_CMD_USB
631#define CONFIG_USB_STORAGE
632#define CONFIG_USB_EHCI
633#define CONFIG_USB_EHCI_FSL
634#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000635#endif
636
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800637#define CONFIG_CMD_EXT2
638
639#define CONFIG_MMC
640
641#ifdef CONFIG_MMC
642#define CONFIG_FSL_ESDHC
643#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
644#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
645#define CONFIG_CMD_MMC
646#define CONFIG_GENERIC_MMC
647#define CONFIG_CMD_EXT2
648#define CONFIG_CMD_FAT
649#define CONFIG_DOS_PARTITION
650#endif
651
652/*
653 * Miscellaneous configurable options
654 */
655#define CONFIG_SYS_LONGHELP /* undef to save memory */
656#define CONFIG_CMDLINE_EDITING /* Command-line editing */
657#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
658#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
659#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
660#ifdef CONFIG_CMD_KGDB
661#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
662#else
663#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
664#endif
665/* Print Buffer Size */
666#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
667 sizeof(CONFIG_SYS_PROMPT)+16)
668#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
669/* Boot Argument Buffer Size */
670#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
671#define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
672
673/*
674 * For booting Linux, the board info and command line data
675 * have to be in the first 64 MB of memory, since this is
676 * the maximum mapped by the Linux kernel during initialization.
677 */
678#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
679#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
680
681#ifdef CONFIG_CMD_KGDB
682#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
683#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
684#endif
685
686/*
687 * Environment Configuration
688 */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000689#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000690#define CONFIG_BOOTFILE "uImage"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800691#define CONFIG_UBOOTPATH u-boot.bin
692
693/* default location for tftp and bootm */
694#define CONFIG_LOADADDR 1000000
695
696#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
697
698#define CONFIG_BAUDRATE 115200
699
700#define __USB_PHY_TYPE utmi
701
702#define CONFIG_EXTRA_ENV_SETTINGS \
703 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
704 "bank_intlv=cs0_cs1\0" \
705 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200706 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
707 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800708 "tftpflash=tftpboot $loadaddr $uboot && " \
709 "protect off $ubootaddr +$filesize && " \
710 "erase $ubootaddr +$filesize && " \
711 "cp.b $loadaddr $ubootaddr $filesize && " \
712 "protect on $ubootaddr +$filesize && " \
713 "cmp.b $loadaddr $ubootaddr $filesize\0" \
714 "consoledev=ttyS0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200715 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800716 "usb_dr_mode=host\0" \
717 "ramdiskaddr=2000000\0" \
718 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
719 "fdtaddr=c00000\0" \
720 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
721 "bdev=sda3\0" \
722 "c=ffe\0"
723
724#define CONFIG_HDBOOT \
725 "setenv bootargs root=/dev/$bdev rw " \
726 "console=$consoledev,$baudrate $othbootargs;" \
727 "tftp $loadaddr $bootfile;" \
728 "tftp $fdtaddr $fdtfile;" \
729 "bootm $loadaddr - $fdtaddr"
730
731#define CONFIG_NFSBOOTCOMMAND \
732 "setenv bootargs root=/dev/nfs rw " \
733 "nfsroot=$serverip:$rootpath " \
734 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
735 "console=$consoledev,$baudrate $othbootargs;" \
736 "tftp $loadaddr $bootfile;" \
737 "tftp $fdtaddr $fdtfile;" \
738 "bootm $loadaddr - $fdtaddr"
739
740#define CONFIG_RAMBOOTCOMMAND \
741 "setenv bootargs root=/dev/ram rw " \
742 "console=$consoledev,$baudrate $othbootargs;" \
743 "tftp $ramdiskaddr $ramdiskfile;" \
744 "tftp $loadaddr $bootfile;" \
745 "tftp $fdtaddr $fdtfile;" \
746 "bootm $loadaddr $ramdiskaddr $fdtaddr"
747
748#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
749
750#ifdef CONFIG_SECURE_BOOT
751#include <asm/fsl_secure_boot.h>
752#endif
753
754#endif /* __CONFIG_H */