blob: 5e09a39bab589462b671d483e9ab5e10eb5e27fe [file] [log] [blame]
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +09001/*
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +09002 modified from SH-IPL+g
3 Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
4
Wolfgang Denk61fb15c52007-12-27 01:52:50 +01005 Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
6
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +09007 Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
8
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090026*/
27
28#include <config.h>
29#include <version.h>
30
31#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010032#include <asm/macro.h>
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090033
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090034#ifdef CONFIG_CPU_SH7751
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +010035#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
36#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090037#ifdef CONFIG_MARUBUN_PCCARD
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +010038#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
39 A3:2 A2:15 A1:15 A0:6 A0B:7 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090040#else /* CONFIG_MARUBUN_PCCARD */
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +010041#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
42 A3:2 A2:15 A1:15 A0:6 A0B:7 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090043#endif /* CONFIG_MARUBUN_PCCARD */
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +010044#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
45 A2: 1-3 A1: 1-3 A0: 0-1 */
46#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
47#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
48#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
49#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090050#else /* CONFIG_CPU_SH7751 */
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +010051#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
52#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
53#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
54 A3:2 A2:15 A1:15 A0:15 A0B:7 */
55#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
56 A2: 1-3 A1: 1-3 A0: 0-1 */
57#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
58#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
59#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
60#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090061#endif /* CONFIG_CPU_SH7751 */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090062
63 .global lowlevel_init
64 .text
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +010065 .align 2
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090066
67lowlevel_init:
68
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010069 write32 CCR_A, CCR_D_DISABLE
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090070
71init_bsc:
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010072 write16 FRQCR_A, FRQCR_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090073
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010074 write32 BCR1_A, BCR1_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090075
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010076 write16 BCR2_A, BCR2_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090077
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010078 write32 WCR1_A, WCR1_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090079
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010080 write32 WCR2_A, WCR2_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090081
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010082 write32 WCR3_A, WCR3_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090083
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010084 write32 MCR_A, MCR_D1
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090085
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010086 /* Set SDRAM mode */
Nobuhiro Iwamatsuc9935c92009-01-11 17:48:56 +090087 write8 SDMR3_A, SDMR3_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090088
Wolfgang Denk61fb15c52007-12-27 01:52:50 +010089 ! Do you need PCMCIA setting?
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090090 ! If so, please add the lines here...
91
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010092 write16 RTCNT_A, RTCNT_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090093
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010094 write16 RTCOR_A, RTCOR_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090095
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010096 write16 RTCSR_A, RTCSR_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090097
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +010098 write16 RFCR_A, RFCR_D
99
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900100 /* Wait DRAM refresh 30 times */
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100101 mov #30, r3
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +09001021:
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100103 mov.w @r1, r0
104 extu.w r0, r2
105 cmp/hi r3, r2
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900106 bf 1b
107
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100108 write32 MCR_A, MCR_D2
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900109
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100110 /* Set SDRAM mode */
Nobuhiro Iwamatsuc9935c92009-01-11 17:48:56 +0900111 write8 SDMR3_A, SDMR3_D
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900112
113 rts
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100114 nop
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900115
116 .align 2
117
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100118CCR_A: .long CCR
119CCR_D_DISABLE: .long 0x0808
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900120FRQCR_A: .long FRQCR
121FRQCR_D:
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +0900122#ifdef CONFIG_CPU_TYPE_R
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900123 .long 0x00000e1a /* 12:3:3 */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +0900124#else /* CONFIG_CPU_TYPE_R */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900125#ifdef CONFIG_GOOD_SESH4
126 .long 0x00000e13 /* 6:2:1 */
127#else
128 .long 0x00000e23 /* 6:1:1 */
129#endif
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +0900130#endif /* CONFIG_CPU_TYPE_R */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900131
132BCR1_A: .long BCR1
133BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
134BCR2_A: .long BCR2
135BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
136WCR1_A: .long WCR1
137WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
138WCR2_A: .long WCR2
139WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
140WCR3_A: .long WCR3
141WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
Wolfgang Denk61fb15c52007-12-27 01:52:50 +0100142RTCSR_A: .long RTCSR
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900143RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
144RTCNT_A: .long RTCNT
145RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
146RTCOR_A: .long RTCOR
147RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
148SDMR3_A: .long SDMR3_ADDRESS
Nobuhiro Iwamatsuc9935c92009-01-11 17:48:56 +0900149SDMR3_D: .long 0x00
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +0900150MCR_A: .long MCR
151MCR_D1: .long MCR_D1_VALUE
152MCR_D2: .long MCR_D2_VALUE
153RFCR_A: .long RFCR
154RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */