| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Port Masks |
| 3 | */ |
| 4 | |
| 5 | #ifndef __BFIN_PERIPHERAL_PORT__ |
| 6 | #define __BFIN_PERIPHERAL_PORT__ |
| 7 | |
| 8 | /* PORTx_MUX Masks */ |
| 9 | #define PORT_x_MUX_0_MASK 0x00000003 |
| 10 | #define PORT_x_MUX_1_MASK 0x0000000C |
| 11 | #define PORT_x_MUX_2_MASK 0x00000030 |
| 12 | #define PORT_x_MUX_3_MASK 0x000000C0 |
| 13 | #define PORT_x_MUX_4_MASK 0x00000300 |
| 14 | #define PORT_x_MUX_5_MASK 0x00000C00 |
| 15 | #define PORT_x_MUX_6_MASK 0x00003000 |
| 16 | #define PORT_x_MUX_7_MASK 0x0000C000 |
| 17 | #define PORT_x_MUX_8_MASK 0x00030000 |
| 18 | #define PORT_x_MUX_9_MASK 0x000C0000 |
| 19 | #define PORT_x_MUX_10_MASK 0x00300000 |
| 20 | #define PORT_x_MUX_11_MASK 0x00C00000 |
| 21 | #define PORT_x_MUX_12_MASK 0x03000000 |
| 22 | #define PORT_x_MUX_13_MASK 0x0C000000 |
| 23 | #define PORT_x_MUX_14_MASK 0x30000000 |
| 24 | #define PORT_x_MUX_15_MASK 0xC0000000 |
| 25 | |
| 26 | #define PORT_x_MUX_FUNC_1 (0x0) |
| 27 | #define PORT_x_MUX_FUNC_2 (0x1) |
| 28 | #define PORT_x_MUX_FUNC_3 (0x2) |
| 29 | #define PORT_x_MUX_FUNC_4 (0x3) |
| 30 | #define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0) |
| 31 | #define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0) |
| 32 | #define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0) |
| 33 | #define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0) |
| 34 | #define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2) |
| 35 | #define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2) |
| 36 | #define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2) |
| 37 | #define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2) |
| 38 | #define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4) |
| 39 | #define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4) |
| 40 | #define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4) |
| 41 | #define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4) |
| 42 | #define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6) |
| 43 | #define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6) |
| 44 | #define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6) |
| 45 | #define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6) |
| 46 | #define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8) |
| 47 | #define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8) |
| 48 | #define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8) |
| 49 | #define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8) |
| 50 | #define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10) |
| 51 | #define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10) |
| 52 | #define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10) |
| 53 | #define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10) |
| 54 | #define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12) |
| 55 | #define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12) |
| 56 | #define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12) |
| 57 | #define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12) |
| 58 | #define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) |
| 59 | #define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) |
| 60 | #define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) |
| 61 | #define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) |
| Ben Maan | 2e5cbe5 | 2008-08-07 13:14:21 -0400 | [diff] [blame] | 62 | #define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16) |
| 63 | #define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16) |
| 64 | #define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16) |
| 65 | #define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16) |
| 66 | #define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18) |
| 67 | #define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18) |
| 68 | #define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18) |
| 69 | #define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18) |
| 70 | #define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20) |
| 71 | #define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20) |
| 72 | #define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20) |
| 73 | #define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20) |
| 74 | #define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22) |
| 75 | #define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22) |
| 76 | #define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22) |
| 77 | #define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22) |
| 78 | #define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24) |
| 79 | #define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24) |
| 80 | #define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24) |
| 81 | #define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24) |
| 82 | #define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26) |
| 83 | #define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26) |
| 84 | #define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26) |
| 85 | #define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26) |
| 86 | #define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28) |
| 87 | #define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28) |
| 88 | #define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28) |
| 89 | #define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28) |
| 90 | #define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30) |
| 91 | #define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30) |
| 92 | #define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30) |
| 93 | #define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30) |
| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 94 | |
| 95 | /* Port A Masks */ |
| 96 | #define PA0 0x0001 |
| 97 | #define PA1 0x0002 |
| 98 | #define PA2 0x0004 |
| 99 | #define PA3 0x0008 |
| 100 | #define PA4 0x0010 |
| 101 | #define PA5 0x0020 |
| 102 | #define PA6 0x0040 |
| 103 | #define PA7 0x0080 |
| 104 | #define PA8 0x0100 |
| 105 | #define PA9 0x0200 |
| 106 | #define PA10 0x0400 |
| 107 | #define PA11 0x0800 |
| 108 | #define PA12 0x1000 |
| 109 | #define PA13 0x2000 |
| 110 | #define PA14 0x4000 |
| 111 | #define PA15 0x8000 |
| 112 | |
| 113 | /* Port B Masks */ |
| 114 | #define PB0 0x0001 |
| 115 | #define PB1 0x0002 |
| 116 | #define PB2 0x0004 |
| 117 | #define PB3 0x0008 |
| 118 | #define PB4 0x0010 |
| 119 | #define PB5 0x0020 |
| 120 | #define PB6 0x0040 |
| 121 | #define PB7 0x0080 |
| 122 | #define PB8 0x0100 |
| 123 | #define PB9 0x0200 |
| 124 | #define PB10 0x0400 |
| 125 | #define PB11 0x0800 |
| 126 | #define PB12 0x1000 |
| 127 | #define PB13 0x2000 |
| 128 | #define PB14 0x4000 |
| 129 | #define PB15 0x8000 |
| 130 | |
| 131 | /* Port C Masks */ |
| 132 | #define PC0 0x0001 |
| 133 | #define PC1 0x0002 |
| 134 | #define PC2 0x0004 |
| 135 | #define PC3 0x0008 |
| 136 | #define PC4 0x0010 |
| 137 | #define PC5 0x0020 |
| 138 | #define PC6 0x0040 |
| 139 | #define PC7 0x0080 |
| 140 | #define PC8 0x0100 |
| 141 | #define PC9 0x0200 |
| 142 | #define PC10 0x0400 |
| 143 | #define PC11 0x0800 |
| 144 | #define PC12 0x1000 |
| 145 | #define PC13 0x2000 |
| 146 | #define PC14 0x4000 |
| 147 | #define PC15 0x8000 |
| 148 | |
| 149 | /* Port F Masks */ |
| 150 | #define PD0 0x0001 |
| 151 | #define PD1 0x0002 |
| 152 | #define PD2 0x0004 |
| 153 | #define PD3 0x0008 |
| 154 | #define PD4 0x0010 |
| 155 | #define PD5 0x0020 |
| 156 | #define PD6 0x0040 |
| 157 | #define PD7 0x0080 |
| 158 | #define PD8 0x0100 |
| 159 | #define PD9 0x0200 |
| 160 | #define PD10 0x0400 |
| 161 | #define PD11 0x0800 |
| 162 | #define PD12 0x1000 |
| 163 | #define PD13 0x2000 |
| 164 | #define PD14 0x4000 |
| 165 | #define PD15 0x8000 |
| 166 | |
| 167 | /* Port F Masks */ |
| 168 | #define PE0 0x0001 |
| 169 | #define PE1 0x0002 |
| 170 | #define PE2 0x0004 |
| 171 | #define PE3 0x0008 |
| 172 | #define PE4 0x0010 |
| 173 | #define PE5 0x0020 |
| 174 | #define PE6 0x0040 |
| 175 | #define PE7 0x0080 |
| 176 | #define PE8 0x0100 |
| 177 | #define PE9 0x0200 |
| 178 | #define PE10 0x0400 |
| 179 | #define PE11 0x0800 |
| 180 | #define PE12 0x1000 |
| 181 | #define PE13 0x2000 |
| 182 | #define PE14 0x4000 |
| 183 | #define PE15 0x8000 |
| 184 | |
| 185 | /* Port F Masks */ |
| 186 | #define PF0 0x0001 |
| 187 | #define PF1 0x0002 |
| 188 | #define PF2 0x0004 |
| 189 | #define PF3 0x0008 |
| 190 | #define PF4 0x0010 |
| 191 | #define PF5 0x0020 |
| 192 | #define PF6 0x0040 |
| 193 | #define PF7 0x0080 |
| 194 | #define PF8 0x0100 |
| 195 | #define PF9 0x0200 |
| 196 | #define PF10 0x0400 |
| 197 | #define PF11 0x0800 |
| 198 | #define PF12 0x1000 |
| 199 | #define PF13 0x2000 |
| 200 | #define PF14 0x4000 |
| 201 | #define PF15 0x8000 |
| 202 | |
| 203 | /* Port G Masks */ |
| 204 | #define PG0 0x0001 |
| 205 | #define PG1 0x0002 |
| 206 | #define PG2 0x0004 |
| 207 | #define PG3 0x0008 |
| 208 | #define PG4 0x0010 |
| 209 | #define PG5 0x0020 |
| 210 | #define PG6 0x0040 |
| 211 | #define PG7 0x0080 |
| 212 | #define PG8 0x0100 |
| 213 | #define PG9 0x0200 |
| 214 | #define PG10 0x0400 |
| 215 | #define PG11 0x0800 |
| 216 | #define PG12 0x1000 |
| 217 | #define PG13 0x2000 |
| 218 | #define PG14 0x4000 |
| 219 | #define PG15 0x8000 |
| 220 | |
| 221 | /* Port H Masks */ |
| 222 | #define PH0 0x0001 |
| 223 | #define PH1 0x0002 |
| 224 | #define PH2 0x0004 |
| 225 | #define PH3 0x0008 |
| 226 | #define PH4 0x0010 |
| 227 | #define PH5 0x0020 |
| 228 | #define PH6 0x0040 |
| 229 | #define PH7 0x0080 |
| 230 | #define PH8 0x0100 |
| 231 | #define PH9 0x0200 |
| 232 | #define PH10 0x0400 |
| 233 | #define PH11 0x0800 |
| 234 | #define PH12 0x1000 |
| 235 | #define PH13 0x2000 |
| 236 | #define PH14 0x4000 |
| 237 | #define PH15 0x8000 |
| 238 | |
| 239 | /* Port J Masks */ |
| 240 | #define PJ0 0x0001 |
| 241 | #define PJ1 0x0002 |
| 242 | #define PJ2 0x0004 |
| 243 | #define PJ3 0x0008 |
| 244 | #define PJ4 0x0010 |
| 245 | #define PJ5 0x0020 |
| 246 | #define PJ6 0x0040 |
| 247 | #define PJ7 0x0080 |
| 248 | #define PJ8 0x0100 |
| 249 | #define PJ9 0x0200 |
| 250 | #define PJ10 0x0400 |
| 251 | #define PJ11 0x0800 |
| 252 | #define PJ12 0x1000 |
| 253 | #define PJ13 0x2000 |
| 254 | #define PJ14 0x4000 |
| 255 | #define PJ15 0x8000 |
| 256 | |
| 257 | #endif |