Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Rini | 03de305 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 7 | #include <config.h> |
Simon Glass | 36bf446 | 2019-11-14 12:57:42 -0700 | [diff] [blame] | 8 | #include <irq_func.h> |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 9 | |
| 10 | /* |
| 11 | * CPU test |
| 12 | * Ternary instructions instr rA,rS,UIMM |
| 13 | * |
| 14 | * Logic instructions: ori, oris, xori, xoris |
| 15 | * |
| 16 | * The test contains a pre-built table of instructions, operands and |
| 17 | * expected results. For each table entry, the test will cyclically use |
| 18 | * different sets of operand registers and result registers. |
| 19 | */ |
| 20 | |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 21 | #include <post.h> |
| 22 | #include "cpu_asm.h" |
| 23 | |
Tom Rini | 1e01950 | 2022-12-04 10:14:17 -0500 | [diff] [blame] | 24 | #if CFG_POST & CFG_SYS_POST_CPU |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 25 | |
| 26 | extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); |
| 27 | extern ulong cpu_post_makecr (long v); |
| 28 | |
| 29 | static struct cpu_post_threei_s |
| 30 | { |
| 31 | ulong cmd; |
| 32 | ulong op1; |
| 33 | ushort op2; |
| 34 | ulong res; |
| 35 | } cpu_post_threei_table[] = |
| 36 | { |
| 37 | { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 38 | OP_ORI, |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 39 | 0x80000000, |
| 40 | 0xffff, |
| 41 | 0x8000ffff |
| 42 | }, |
| 43 | { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 44 | OP_ORIS, |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 45 | 0x00008000, |
| 46 | 0xffff, |
| 47 | 0xffff8000 |
| 48 | }, |
| 49 | { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 50 | OP_XORI, |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 51 | 0x8000ffff, |
| 52 | 0xffff, |
| 53 | 0x80000000 |
| 54 | }, |
| 55 | { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 56 | OP_XORIS, |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 57 | 0x00008000, |
| 58 | 0xffff, |
| 59 | 0xffff8000 |
| 60 | }, |
| 61 | }; |
Mike Frysinger | d239781 | 2011-05-10 07:28:35 +0000 | [diff] [blame] | 62 | static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table); |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 63 | |
| 64 | int cpu_post_test_threei (void) |
| 65 | { |
| 66 | int ret = 0; |
| 67 | unsigned int i, reg; |
| 68 | int flag = disable_interrupts(); |
| 69 | |
| 70 | for (i = 0; i < cpu_post_threei_size && ret == 0; i++) |
| 71 | { |
| 72 | struct cpu_post_threei_s *test = cpu_post_threei_table + i; |
| 73 | |
| 74 | for (reg = 0; reg < 32 && ret == 0; reg++) |
| 75 | { |
| 76 | unsigned int reg0 = (reg + 0) % 32; |
| 77 | unsigned int reg1 = (reg + 1) % 32; |
| 78 | unsigned int stk = reg < 16 ? 31 : 15; |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 79 | unsigned long code[] = |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 80 | { |
| 81 | ASM_STW(stk, 1, -4), |
| 82 | ASM_ADDI(stk, 1, -16), |
| 83 | ASM_STW(3, stk, 8), |
| 84 | ASM_STW(reg0, stk, 4), |
| 85 | ASM_STW(reg1, stk, 0), |
| 86 | ASM_LWZ(reg0, stk, 8), |
| 87 | ASM_11IX(test->cmd, reg1, reg0, test->op2), |
| 88 | ASM_STW(reg1, stk, 8), |
| 89 | ASM_LWZ(reg1, stk, 0), |
| 90 | ASM_LWZ(reg0, stk, 4), |
| 91 | ASM_LWZ(3, stk, 8), |
| 92 | ASM_ADDI(1, stk, 16), |
| 93 | ASM_LWZ(stk, 1, -4), |
| 94 | ASM_BLR, |
| 95 | }; |
| 96 | ulong res; |
| 97 | ulong cr; |
| 98 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 99 | cr = 0; |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 100 | cpu_post_exec_21 (code, & cr, & res, test->op1); |
| 101 | |
| 102 | ret = res == test->res && cr == 0 ? 0 : -1; |
| 103 | |
| 104 | if (ret != 0) |
| 105 | { |
Wolfgang Denk | 93e1459 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 106 | post_log ("Error at threei test %d !\n", i); |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 107 | } |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | if (flag) |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 112 | enable_interrupts(); |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 113 | |
| 114 | return ret; |
| 115 | } |
| 116 | |
| 117 | #endif |