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Wolfgang Denk645da512005-10-05 02:00:09 +02001/*
2 * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
3 * Anders Larsen <alarsen@rea.de>
4 *
5 * Configuation settings for the Cogent CSB637 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/* ARM asynchronous clock */
30#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
31#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */
32
33#define AT91_SLOW_CLOCK 32768 /* slow clock */
34
35#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
Wolfgang Denkf5c254d2005-10-06 01:26:16 +020037#define CONFIG_CSB637 1 /* on a CSB637 board */
Wolfgang Denk645da512005-10-05 02:00:09 +020038#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39#define USE_920T_MMU 1
40
41#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42#define CONFIG_SETUP_MEMORY_TAGS 1
43#define CONFIG_INITRD_TAG 1
44
45#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
Wolfgang Denk645da512005-10-05 02:00:09 +020047/* flash */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010048#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
49#define CONFIG_SYS_MC_PUP_VAL 0x00000000
50#define CONFIG_SYS_MC_PUER_VAL 0x00000000
51#define CONFIG_SYS_MC_ASR_VAL 0x00000000
52#define CONFIG_SYS_MC_AASR_VAL 0x00000000
53#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
54#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
Wolfgang Denk645da512005-10-05 02:00:09 +020055
56/* clocks */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010057#define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
58#define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
59#define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
Wolfgang Denk645da512005-10-05 02:00:09 +020060
61/* sdram */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010062#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
64#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
65#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
66#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */
67#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
68#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
69#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
70#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
71#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
72#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
Jens Scharsig80523522008-11-18 10:48:46 +010075#else
76#define CONFIG_SKIP_RELOCATE_UBOOT
Wolfgang Denk645da512005-10-05 02:00:09 +020077#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
78/*
79 * Size of malloc() pool
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
82#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
Wolfgang Denk645da512005-10-05 02:00:09 +020083
Wolfgang Denkf5c254d2005-10-06 01:26:16 +020084#define CONFIG_BAUDRATE 115200
Wolfgang Denk645da512005-10-05 02:00:09 +020085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
Wolfgang Denk645da512005-10-05 02:00:09 +020087
88/*
89 * Hardware drivers
90 */
91
92/* define one of these to choose the DBGU, USART0 or USART1 as console */
Jean-Christophe PLAGNIOL-VILLARDbeebd852009-03-27 23:26:43 +010093#define CONFIG_AT91RM9200_USART
Wolfgang Denk645da512005-10-05 02:00:09 +020094#define CONFIG_DBGU
95#undef CONFIG_USART0
96#undef CONFIG_USART1
97
98#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
99
100#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
101
102#define CONFIG_BOOTDELAY 3
103/* #define CONFIG_ENV_OVERWRITE 1 */
104
Wolfgang Denk645da512005-10-05 02:00:09 +0200105
Jon Loeliger37e4f242007-07-04 22:31:56 -0500106/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500107 * BOOTP options
108 */
109#define CONFIG_BOOTP_BOOTFILESIZE
110#define CONFIG_BOOTP_BOOTPATH
111#define CONFIG_BOOTP_GATEWAY
112#define CONFIG_BOOTP_HOSTNAME
113
114
115/*
Jon Loeliger37e4f242007-07-04 22:31:56 -0500116 * Command line configuration.
117 */
118#include <config_cmd_default.h>
119
Jon Loeliger37e4f242007-07-04 22:31:56 -0500120#define CONFIG_CMD_DHCP
Wolfgang Denk3c959602008-07-31 10:12:09 +0200121#define CONFIG_CMD_JFFS2
Jon Loeliger37e4f242007-07-04 22:31:56 -0500122#define CONFIG_CMD_PING
123
Wolfgang Denk3c959602008-07-31 10:12:09 +0200124#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */
Wolfgang Denk645da512005-10-05 02:00:09 +0200125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Wolfgang Denk645da512005-10-05 02:00:09 +0200127#define SECTORSIZE 512
128
129#define ADDR_COLUMN 1
130#define ADDR_PAGE 2
131#define ADDR_COLUMN_PAGE 3
132
133#define NAND_ChipID_UNKNOWN 0x00
134#define NAND_MAX_FLOORS 1
Wolfgang Denk645da512005-10-05 02:00:09 +0200135
136#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
137#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
138
Wolfgang Denk3c959602008-07-31 10:12:09 +0200139#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
Wolfgang Denk645da512005-10-05 02:00:09 +0200140#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
141#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
142
143#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
144
145#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
146#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
147#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
148#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
149/* the following are NOP's in our implementation */
150#define NAND_CTL_CLRALE(nandptr)
151#define NAND_CTL_SETALE(nandptr)
152#define NAND_CTL_CLRCLE(nandptr)
153#define NAND_CTL_SETCLE(nandptr)
154
Wolfgang Denk3c959602008-07-31 10:12:09 +0200155#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */
156
Wolfgang Denk645da512005-10-05 02:00:09 +0200157#define CONFIG_NR_DRAM_BANKS 1
158#define PHYS_SDRAM 0x20000000
159#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
162#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
163#define CONFIG_SYS_ALT_MEMTEST 1
164#define CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4
Wolfgang Denk645da512005-10-05 02:00:09 +0200165
166#define CONFIG_DRIVER_ETHER
167#define CONFIG_NET_RETRY_COUNT 20
168#undef CONFIG_AT91C_USE_RMII
169
170#undef CONFIG_HAS_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
172#define CONFIG_SYS_MAX_DATAFLASH_BANKS 0
173#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
174#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
175#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
Wolfgang Denk645da512005-10-05 02:00:09 +0200176
177/*
178 * FLASH Device configuration
179 */
180#define PHYS_FLASH_1 0x10000000
181#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
183#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200184#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_EMPTY_INFO
186#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
187#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
188#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
189#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
190#define CONFIG_SYS_MAX_FLASH_SECT 64
Wolfgang Denk645da512005-10-05 02:00:09 +0200191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_JFFS2_FIRST_BANK 0
193#define CONFIG_SYS_JFFS2_FIRST_SECTOR 3
194#define CONFIG_SYS_JFFS2_NUM_BANKS 1
Wolfgang Denk645da512005-10-05 02:00:09 +0200195
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200196#undef CONFIG_ENV_IS_IN_DATAFLASH
Wolfgang Denk645da512005-10-05 02:00:09 +0200197
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200198#ifdef CONFIG_ENV_IS_IN_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200199#define CONFIG_ENV_OFFSET 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
Wolfgang Denk645da512005-10-05 02:00:09 +0200202#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200203#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200204#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
205#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200206#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
Wolfgang Denk645da512005-10-05 02:00:09 +0200207
208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
Wolfgang Denk645da512005-10-05 02:00:09 +0200210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
Wolfgang Denk645da512005-10-05 02:00:09 +0200212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
214#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
215#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
216#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
Wolfgang Denk645da512005-10-05 02:00:09 +0200217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_HZ 1000
219#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
Ladislav Michl2c5260f2007-12-06 23:24:57 +0100220 /* AT91C_TC_TIMER_DIV1_CLOCK */
Wolfgang Denk645da512005-10-05 02:00:09 +0200221
222#define CONFIG_STACKSIZE (32*1024) /* regular stack */
223
224#ifdef CONFIG_USE_IRQ
225#error CONFIG_USE_IRQ not supported
226#endif
227
228#endif