Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Texas Instruments |
| 4 | * |
| 5 | * Richard Woodruff <r-woodruff2@ti.com> |
| 6 | * Syed Moahmmed Khasim <khasim@ti.com> |
| 7 | * |
| 8 | * (C) Copyright 2002 |
| 9 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 10 | * Marius Groeger <mgroeger@sysgo.de> |
| 11 | * Alex Zuepke <azu@sysgo.de> |
| 12 | * |
| 13 | * (C) Copyright 2002 |
Detlev Zundel | 792a09e | 2009-05-13 10:54:10 +0200 | [diff] [blame] | 14 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 15 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 16 | * SPDX-License-Identifier: GPL-2.0+ |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <common.h> |
| 20 | #include <asm/io.h> |
Tom Rini | 98f9200 | 2013-03-14 11:15:25 +0000 | [diff] [blame] | 21 | #include <asm/arch/cpu.h> |
Sricharan R | f9b814a | 2013-05-30 03:19:34 +0000 | [diff] [blame] | 22 | #include <asm/arch/clock.h> |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 23 | |
Dirk Behme | b03c840 | 2010-12-11 10:50:48 -0500 | [diff] [blame] | 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
Dirk Behme | 97a099e | 2009-08-08 09:30:21 +0200 | [diff] [blame] | 26 | static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 27 | |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 28 | /* |
| 29 | * Nothing really to do with interrupts, just starts up a counter. |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 30 | */ |
| 31 | |
John Rigby | aadcfc1 | 2010-12-27 14:33:10 +0000 | [diff] [blame] | 32 | #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) |
| 33 | #define TIMER_OVERFLOW_VAL 0xffffffff |
| 34 | #define TIMER_LOAD_VAL 0 |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 35 | |
Jean-Christophe PLAGNIOL-VILLARD | b54384e | 2009-05-15 23:47:02 +0200 | [diff] [blame] | 36 | int timer_init(void) |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 37 | { |
| 38 | /* start the counter ticking up, reload value on overflow */ |
| 39 | writel(TIMER_LOAD_VAL, &timer_base->tldr); |
| 40 | /* enable timer */ |
Ladislav Michl | 81472d8 | 2009-03-30 18:58:41 +0200 | [diff] [blame] | 41 | writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 42 | &timer_base->tclr); |
| 43 | |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | /* |
| 48 | * timer without interrupts |
| 49 | */ |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 50 | ulong get_timer(ulong base) |
| 51 | { |
| 52 | return get_timer_masked() - base; |
| 53 | } |
| 54 | |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 55 | /* delay x useconds */ |
Ingo van Lil | 3eb90ba | 2009-11-24 14:09:21 +0100 | [diff] [blame] | 56 | void __udelay(unsigned long usec) |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 57 | { |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 58 | long tmo = usec * (TIMER_CLOCK / 1000) / 1000; |
| 59 | unsigned long now, last = readl(&timer_base->tcrr); |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 60 | |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 61 | while (tmo > 0) { |
| 62 | now = readl(&timer_base->tcrr); |
| 63 | if (last > now) /* count up timer overflow */ |
John Rigby | aadcfc1 | 2010-12-27 14:33:10 +0000 | [diff] [blame] | 64 | tmo -= TIMER_OVERFLOW_VAL - last + now + 1; |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 65 | else |
| 66 | tmo -= now - last; |
| 67 | last = now; |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 68 | } |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 69 | } |
| 70 | |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 71 | ulong get_timer_masked(void) |
| 72 | { |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 73 | /* current tick value */ |
| 74 | ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 75 | |
Simon Glass | 582601d | 2012-12-13 20:48:35 +0000 | [diff] [blame] | 76 | if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 77 | /* move stamp fordward with absoulte diff ticks */ |
Simon Glass | 582601d | 2012-12-13 20:48:35 +0000 | [diff] [blame] | 78 | gd->arch.tbl += (now - gd->arch.lastinc); |
Simon Glass | 66ee692 | 2012-12-13 20:48:34 +0000 | [diff] [blame] | 79 | } else { /* we have rollover of incrementer */ |
| 80 | gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / |
Simon Glass | 582601d | 2012-12-13 20:48:35 +0000 | [diff] [blame] | 81 | CONFIG_SYS_HZ)) - gd->arch.lastinc) + now; |
Simon Glass | 66ee692 | 2012-12-13 20:48:34 +0000 | [diff] [blame] | 82 | } |
Simon Glass | 582601d | 2012-12-13 20:48:35 +0000 | [diff] [blame] | 83 | gd->arch.lastinc = now; |
Simon Glass | 66ee692 | 2012-12-13 20:48:34 +0000 | [diff] [blame] | 84 | return gd->arch.tbl; |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 85 | } |
| 86 | |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 87 | /* |
| 88 | * This function is derived from PowerPC code (read timebase as long long). |
| 89 | * On ARM it just returns the timer value. |
| 90 | */ |
| 91 | unsigned long long get_ticks(void) |
| 92 | { |
| 93 | return get_timer(0); |
| 94 | } |
| 95 | |
| 96 | /* |
| 97 | * This function is derived from PowerPC code (timebase clock frequency). |
| 98 | * On ARM it returns the number of timer ticks per second. |
| 99 | */ |
| 100 | ulong get_tbclk(void) |
| 101 | { |
Manikandan Pillai | d3a513c | 2009-04-21 17:29:05 +0200 | [diff] [blame] | 102 | return CONFIG_SYS_HZ; |
Dirk Behme | 91eee54 | 2008-12-14 09:47:15 +0100 | [diff] [blame] | 103 | } |