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Stefano Babicf8f8acd2010-07-06 19:32:09 +02001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * Configuration settings for the MX51-3Stack Freescale board.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Stefano Babicf8f8acd2010-07-06 19:32:09 +020027
28#define CONFIG_MX51 /* in a mx51 */
Aneesh Ve47f2db2011-06-16 23:30:48 +000029#define CONFIG_SYS_L2CACHE_OFF
Fabio Estevamc02d8282011-05-10 08:13:56 +000030#define CONFIG_SYS_TEXT_BASE 0x97800000
Stefano Babicf8f8acd2010-07-06 19:32:09 +020031
Liu Hui-R64343595f3e52011-01-03 22:27:35 +000032#include <asm/arch/imx-regs.h>
33
Jason Liuff9f4752010-10-18 11:09:26 +080034#define CONFIG_SYS_MX5_HCLK 24000000
35#define CONFIG_SYS_MX5_CLK32 32768
Stefano Babicf8f8acd2010-07-06 19:32:09 +020036#define CONFIG_DISPLAY_CPUINFO
37#define CONFIG_DISPLAY_BOARDINFO
38
39#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
40#define CONFIG_REVISION_TAG
41#define CONFIG_SETUP_MEMORY_TAGS
42#define CONFIG_INITRD_TAG
43#define BOARD_LATE_INIT
44
45/*
46 * Size of malloc() pool
47 */
48#define CONFIG_SYS_MALLOC_LEN (2048 * 1024)
49
Stefano Babicf8f8acd2010-07-06 19:32:09 +020050/*
51 * Hardware drivers
52 */
53#define CONFIG_MXC_UART
54#define CONFIG_SYS_MX51_UART3
55#define CONFIG_MXC_GPIO
56#define CONFIG_MXC_SPI
57#define CONFIG_HW_WATCHDOG
58
59 /*
60 * SPI Configs
61 * */
62#define CONFIG_FSL_SF
63#define CONFIG_CMD_SF
64
65#define CONFIG_SPI_FLASH
66#define CONFIG_SPI_FLASH_STMICRO
67
68/*
69 * Use gpio 4 pin 25 as chip select for SPI flash
70 * This corresponds to gpio 121
71 */
72#define CONFIG_SPI_FLASH_CS (1 | (121 << 8))
73#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
74#define CONFIG_SF_DEFAULT_SPEED 25000000
75
76#define CONFIG_ENV_SPI_CS (1 | (121 << 8))
77#define CONFIG_ENV_SPI_BUS 0
78#define CONFIG_ENV_SPI_MAX_HZ 25000000
79#define CONFIG_ENV_SPI_MODE SPI_MODE_0
80
81#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
82#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
83#define CONFIG_ENV_SIZE (4 * 1024)
84
85#define CONFIG_FSL_ENV_IN_SF
86#define CONFIG_ENV_IS_IN_SPI_FLASH
87
88/* PMIC Controller */
89#define CONFIG_FSL_PMIC
90#define CONFIG_FSL_PMIC_BUS 0
91#define CONFIG_FSL_PMIC_CS 0
92#define CONFIG_FSL_PMIC_CLK 2500000
93#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
94#define CONFIG_RTC_MC13783
95
96/*
97 * MMC Configs
98 */
99#define CONFIG_FSL_ESDHC
100#ifdef CONFIG_FSL_ESDHC
101#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
102#define CONFIG_SYS_FSL_ESDHC_NUM 1
103
104#define CONFIG_MMC
105
106#define CONFIG_CMD_MMC
107#define CONFIG_GENERIC_MMC
108#define CONFIG_CMD_FAT
109#define CONFIG_DOS_PARTITION
110#endif
111
112#define CONFIG_CMD_DATE
113
114/*
115 * Eth Configs
116 */
117#define CONFIG_HAS_ETH1
118#define CONFIG_NET_MULTI
119#define CONFIG_MII
120#define CONFIG_DISCOVER_PHY
121
122#define CONFIG_FEC_MXC
123#define IMX_FEC_BASE FEC_BASE_ADDR
124#define CONFIG_FEC_MXC_PHYADDR 0x1F
125
126#define CONFIG_CMD_PING
127#define CONFIG_CMD_MII
128#define CONFIG_CMD_NET
129
130/* allow to overwrite serial and ethaddr */
131#define CONFIG_ENV_OVERWRITE
132#define CONFIG_CONS_INDEX 3
133#define CONFIG_BAUDRATE 115200
134#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
135
136/***********************************************************
137 * Command definition
138 ***********************************************************/
139
140#include <config_cmd_default.h>
141
142#define CONFIG_CMD_SPI
143#undef CONFIG_CMD_IMLS
144
145#define CONFIG_BOOTDELAY 3
146
147#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
148
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "netdev=eth0\0" \
151 "loadaddr=0x90800000\0"
152
153/*
154 * Miscellaneous configurable options
155 */
156#define CONFIG_SYS_LONGHELP
157#define CONFIG_SYS_PROMPT "Vision II U-boot > "
158#define CONFIG_AUTO_COMPLETE
159#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
160
161/* Print Buffer Size */
162#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
163 sizeof(CONFIG_SYS_PROMPT) + 16)
164#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
165#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
166
167#define CONFIG_SYS_MEMTEST_START 0x90000000
168#define CONFIG_SYS_MEMTEST_END 0x10000
169
170#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
171
172#define CONFIG_SYS_HZ 1000
173#define CONFIG_CMDLINE_EDITING
174#define CONFIG_SYS_HUSH_PARSER
175#define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > "
176
177/*
178 * Stack sizes
179 */
180#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
181
182/*
183 * Physical Memory Map
184 */
185#define CONFIG_NR_DRAM_BANKS 2
186#define PHYS_SDRAM_1 CSD0_BASE_ADDR
187#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
188#define PHYS_SDRAM_2 CSD1_BASE_ADDR
189#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
190#define CONFIG_SYS_SDRAM_BASE 0x90000000
191#define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000
192
Wolfgang Denk553f0982010-10-26 13:32:32 +0200193#define CONFIG_SYS_INIT_RAM_SIZE (64 * 1024)
194#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200195 GENERATED_GBL_DATA_SIZE)
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200196#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
197 CONFIG_SYS_GBL_DATA_OFFSET)
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200198#define CONFIG_BOARD_EARLY_INIT_F
199
200/* 166 MHz DDR RAM */
201#define CONFIG_SYS_DDR_CLKSEL 0
202#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
203
204#define CONFIG_SYS_NO_FLASH
205
Stefano Babica0152c42010-10-21 10:34:39 +0200206/*
207 * Framebuffer and LCD
208 */
209#define CONFIG_PREBOOT
210#define CONFIG_LCD
211#define CONFIG_VIDEO_MX5
212#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
213#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
214#define CONFIG_SYS_CONSOLE_IS_IN_ENV
215#define LCD_BPP LCD_COLOR16
216#define CONFIG_SPLASH_SCREEN
217#define CONFIG_CMD_BMP
218#define CONFIG_BMP_16BPP
219
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200220#endif /* __CONFIG_H */