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wdenk04a85b32004-04-15 18:22:41 +00001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
wdenkc26e4542004-04-18 10:13:26 +000032#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
33#error Unsupported CONFIG_NETPHONE version
34#endif
35
wdenk04a85b32004-04-15 18:22:41 +000036/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
42#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */
43
44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47
48#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
49
50/* #define CONFIG_XIN 10000000 */
51#define CONFIG_XIN 50000000
wdenk79fa88f2004-06-07 23:46:25 +000052/* #define MPC8XX_HZ 120000000 */
53#define MPC8XX_HZ 66666666
wdenk04a85b32004-04-15 18:22:41 +000054
55#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56
57#if 0
58#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59#else
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61#endif
62
63#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
64
65#define CONFIG_PREBOOT "echo;"
66
67#undef CONFIG_BOOTARGS
68#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020069 "tftpboot; " \
wdenk79fa88f2004-06-07 23:46:25 +000070 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk04a85b32004-04-15 18:22:41 +000072 "bootm"
73
74#define CONFIG_AUTOSCRIPT
75#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk04a85b32004-04-15 18:22:41 +000077
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
84
Jon Loeliger7be044e2007-07-09 21:24:19 -050085/*
86 * BOOTP options
87 */
88#define CONFIG_BOOTP_SUBNETMASK
89#define CONFIG_BOOTP_GATEWAY
90#define CONFIG_BOOTP_HOSTNAME
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_BOOTFILESIZE
93#define CONFIG_BOOTP_NISDOMAIN
wdenk04a85b32004-04-15 18:22:41 +000094
95#undef CONFIG_MAC_PARTITION
96#undef CONFIG_DOS_PARTITION
97
98#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
99
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200100#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
wdenk04a85b32004-04-15 18:22:41 +0000101#define FEC_ENET 1 /* eth.c needs it that way... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#undef CONFIG_SYS_DISCOVER_PHY
wdenk04a85b32004-04-15 18:22:41 +0000103#define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500104#define CONFIG_MII_INIT 1
wdenk04a85b32004-04-15 18:22:41 +0000105#define CONFIG_RMII 1 /* use RMII interface */
106
107#define CONFIG_ETHER_ON_FEC1 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200108#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
wdenk04a85b32004-04-15 18:22:41 +0000109#define CONFIG_FEC1_PHY_NORXERR 1
110
111#define CONFIG_ETHER_ON_FEC2 1
112#define CONFIG_FEC2_PHY 4
113#define CONFIG_FEC2_PHY_NORXERR 1
114
115#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
116
Jon Loeligere18a1062007-07-08 14:21:43 -0500117
118/*
119 * Command line configuration.
120 */
121#include <config_cmd_default.h>
122
123#define CONFIG_CMD_NAND
124#define CONFIG_CMD_DHCP
125#define CONFIG_CMD_PING
126#define CONFIG_CMD_MII
127#define CONFIG_CMD_CDP
128
wdenk04a85b32004-04-15 18:22:41 +0000129
130#define CONFIG_BOARD_EARLY_INIT_F 1
131#define CONFIG_MISC_INIT_R
132
wdenk04a85b32004-04-15 18:22:41 +0000133/*
134 * Miscellaneous configurable options
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk04a85b32004-04-15 18:22:41 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_HUSH_PARSER 1
140#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk04a85b32004-04-15 18:22:41 +0000141
Jon Loeligere18a1062007-07-08 14:21:43 -0500142#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk04a85b32004-04-15 18:22:41 +0000144#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk04a85b32004-04-15 18:22:41 +0000146#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
148#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
149#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk04a85b32004-04-15 18:22:41 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
152#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
wdenk04a85b32004-04-15 18:22:41 +0000153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk04a85b32004-04-15 18:22:41 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk04a85b32004-04-15 18:22:41 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk04a85b32004-04-15 18:22:41 +0000159
160/*
161 * Low Level Configuration Settings
162 * (address mappings, register initial values, etc.)
163 * You should know what you are doing if you make changes here.
164 */
165/*-----------------------------------------------------------------------
166 * Internal Memory Mapped Register
167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_IMMR 0xFF000000
wdenk04a85b32004-04-15 18:22:41 +0000169
170/*-----------------------------------------------------------------------
171 * Definitions for initial stack pointer and data area (in DPRAM)
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
174#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
175#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
176#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
177#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk04a85b32004-04-15 18:22:41 +0000178
179/*-----------------------------------------------------------------------
180 * Start addresses for the final memory configuration
181 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk04a85b32004-04-15 18:22:41 +0000183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_SDRAM_BASE 0x00000000
185#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenk04a85b32004-04-15 18:22:41 +0000186#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk04a85b32004-04-15 18:22:41 +0000188#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk04a85b32004-04-15 18:22:41 +0000190#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
192#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc26e4542004-04-18 10:13:26 +0000193#if CONFIG_NETPHONE_VERSION == 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_BASE4 0x40080000
wdenkc26e4542004-04-18 10:13:26 +0000195#endif
196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_RESET_ADDRESS 0x80000000
wdenk04a85b32004-04-15 18:22:41 +0000198
199/*
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk04a85b32004-04-15 18:22:41 +0000205
206/*-----------------------------------------------------------------------
207 * FLASH organization
208 */
wdenkc26e4542004-04-18 10:13:26 +0000209#if CONFIG_NETPHONE_VERSION == 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenkc26e4542004-04-18 10:13:26 +0000211#elif CONFIG_NETPHONE_VERSION == 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenkc26e4542004-04-18 10:13:26 +0000213#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk04a85b32004-04-15 18:22:41 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
217#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk04a85b32004-04-15 18:22:41 +0000218
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200219#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200220#define CONFIG_ENV_SECT_SIZE 0x10000
wdenk04a85b32004-04-15 18:22:41 +0000221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_OFFSET 0
224#define CONFIG_ENV_SIZE 0x4000
wdenk04a85b32004-04-15 18:22:41 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200227#define CONFIG_ENV_OFFSET_REDUND 0
228#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
wdenk04a85b32004-04-15 18:22:41 +0000229
230/*-----------------------------------------------------------------------
231 * Cache Configuration
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere18a1062007-07-08 14:21:43 -0500234#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk04a85b32004-04-15 18:22:41 +0000236#endif
237
238/*-----------------------------------------------------------------------
239 * SYPCR - System Protection Control 11-9
240 * SYPCR can only be written once after reset!
241 *-----------------------------------------------------------------------
242 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
243 */
244#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk04a85b32004-04-15 18:22:41 +0000246 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
247#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk04a85b32004-04-15 18:22:41 +0000249#endif
250
251/*-----------------------------------------------------------------------
252 * SIUMCR - SIU Module Configuration 11-6
253 *-----------------------------------------------------------------------
254 * PCMCIA config., multi-function pin tri-state
255 */
256#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
wdenk04a85b32004-04-15 18:22:41 +0000258#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
wdenk04a85b32004-04-15 18:22:41 +0000260#endif /* CONFIG_CAN_DRIVER */
261
262/*-----------------------------------------------------------------------
263 * TBSCR - Time Base Status and Control 11-26
264 *-----------------------------------------------------------------------
265 * Clear Reference Interrupt Status, Timebase freezing enabled
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk04a85b32004-04-15 18:22:41 +0000268
269/*-----------------------------------------------------------------------
270 * RTCSC - Real-Time Clock Status and Control Register 11-27
271 *-----------------------------------------------------------------------
272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk04a85b32004-04-15 18:22:41 +0000274
275/*-----------------------------------------------------------------------
276 * PISCR - Periodic Interrupt Status and Control 11-31
277 *-----------------------------------------------------------------------
278 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk04a85b32004-04-15 18:22:41 +0000281
282/*-----------------------------------------------------------------------
283 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
284 *-----------------------------------------------------------------------
285 * Reset PLL lock status sticky bit, timer expired status bit and timer
286 * interrupt status bit
287 *
288 */
289
290#if CONFIG_XIN == 10000000
291
292#if MPC8XX_HZ == 120000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000294 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200295 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000296#elif MPC8XX_HZ == 100000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000298 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200299 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000300#elif MPC8XX_HZ == 50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000302 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200303 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000304#elif MPC8XX_HZ == 25000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000306 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200307 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000308#elif MPC8XX_HZ == 40000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000310 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200311 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000312#elif MPC8XX_HZ == 75000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000314 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200315 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000316#else
317#error unsupported CPU freq for XIN = 10MHz
318#endif
319
320#elif CONFIG_XIN == 50000000
321
322#if MPC8XX_HZ == 120000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000324 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200325 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000326#elif MPC8XX_HZ == 100000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenk04a85b32004-04-15 18:22:41 +0000328 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200329 PLPRCR_TEXPS)
wdenkc26e4542004-04-18 10:13:26 +0000330#elif MPC8XX_HZ == 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
wdenkc26e4542004-04-18 10:13:26 +0000332 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200333 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000334#else
335#error unsupported CPU freq for XIN = 50MHz
336#endif
337
338#else
339
340#error unsupported XIN freq
341#endif
342
343
344/*
345 *-----------------------------------------------------------------------
346 * SCCR - System Clock and reset Control Register 15-27
347 *-----------------------------------------------------------------------
348 * Set clock output, timebase and RTC source and divider,
349 * power management and some other internal clocks
wdenk79fa88f2004-06-07 23:46:25 +0000350 *
351 * Note: When TBS == 0 the timebase is independent of current cpu clock.
wdenk04a85b32004-04-15 18:22:41 +0000352 */
353
354#define SCCR_MASK SCCR_EBDF11
355#if MPC8XX_HZ > 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk04a85b32004-04-15 18:22:41 +0000357 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
358 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
359 SCCR_DFALCD00 | SCCR_EBDF01)
360#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk04a85b32004-04-15 18:22:41 +0000362 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
363 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
364 SCCR_DFALCD00)
365#endif
366
367/*-----------------------------------------------------------------------
368 *
369 *-----------------------------------------------------------------------
370 *
371 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372/*#define CONFIG_SYS_DER 0x2002000F*/
373#define CONFIG_SYS_DER 0
wdenk04a85b32004-04-15 18:22:41 +0000374
375/*
376 * Init Memory Controller:
377 *
378 * BR0/1 and OR0/1 (FLASH)
379 */
380
381#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
382
383/* used to re-map FLASH both when starting from SRAM or FLASH:
384 * restrict access enough to keep SRAM working (if any)
385 * but not too much to meddle with FLASH accesses
386 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
388#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk04a85b32004-04-15 18:22:41 +0000389
390/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
wdenk04a85b32004-04-15 18:22:41 +0000392
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
394#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
395#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk04a85b32004-04-15 18:22:41 +0000396
wdenkc26e4542004-04-18 10:13:26 +0000397#if CONFIG_NETPHONE_VERSION == 2
398
399#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
400
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
402#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
403#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenkc26e4542004-04-18 10:13:26 +0000404
405#endif
406
wdenk04a85b32004-04-15 18:22:41 +0000407/*
408 * BR3 and OR3 (SDRAM)
409 *
410 */
411#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
412#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
413
414/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
wdenk04a85b32004-04-15 18:22:41 +0000416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
418#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
wdenk04a85b32004-04-15 18:22:41 +0000419
420/*
421 * Memory Periodic Timer Prescaler
422 */
423
424/*
425 * Memory Periodic Timer Prescaler
426 *
427 * The Divider for PTA (refresh timer) configuration is based on an
428 * example SDRAM configuration (64 MBit, one bank). The adjustment to
429 * the number of chip selects (NCS) and the actually needed refresh
430 * rate is done by setting MPTPR.
431 *
432 * PTA is calculated from
433 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
434 *
435 * gclk CPU clock (not bus clock!)
436 * Trefresh Refresh cycle * 4 (four word bursts used)
437 *
438 * 4096 Rows from SDRAM example configuration
439 * 1000 factor s -> ms
440 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
441 * 4 Number of refresh cycles per period
442 * 64 Refresh cycle in ms per number of rows
443 * --------------------------------------------
444 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
445 *
446 * 50 MHz => 50.000.000 / Divider = 98
447 * 66 Mhz => 66.000.000 / Divider = 129
448 * 80 Mhz => 80.000.000 / Divider = 156
449 */
450
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_MAMR_PTA 234
wdenk04a85b32004-04-15 18:22:41 +0000452
453/*
454 * For 16 MBit, refresh rates could be 31.3 us
455 * (= 64 ms / 2K = 125 / quad bursts).
456 * For a simpler initialization, 15.6 us is used instead.
457 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
459 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk04a85b32004-04-15 18:22:41 +0000460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
462#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk04a85b32004-04-15 18:22:41 +0000463
464/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
466#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk04a85b32004-04-15 18:22:41 +0000467
468/*
469 * MAMR settings for SDRAM
470 */
471
472/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk04a85b32004-04-15 18:22:41 +0000474 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
476
477/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk04a85b32004-04-15 18:22:41 +0000479 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
480 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
481
482/*
483 * Internal Definitions
484 *
485 * Boot Flags
486 */
487#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
488#define BOOTFLAG_WARM 0x02 /* Software reboot */
489
wdenk04a85b32004-04-15 18:22:41 +0000490#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
491
492/****************************************************************/
493
494#define DSP_SIZE 0x00010000 /* 64K */
495#define NAND_SIZE 0x00010000 /* 64K */
wdenk04a85b32004-04-15 18:22:41 +0000496
497#define DSP_BASE 0xF1000000
498#define NAND_BASE 0xF1010000
wdenk04a85b32004-04-15 18:22:41 +0000499
500/****************************************************************/
501
502/* NAND */
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200503#define CONFIG_NAND_LEGACY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_NAND_BASE NAND_BASE
wdenk04a85b32004-04-15 18:22:41 +0000505#define CONFIG_MTD_NAND_ECC_JFFS2
wdenk79fa88f2004-06-07 23:46:25 +0000506#define CONFIG_MTD_NAND_VERIFY_WRITE
507#define CONFIG_MTD_NAND_UNSAFE
wdenk04a85b32004-04-15 18:22:41 +0000508
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_MAX_NAND_DEVICE 1
wdenk04a85b32004-04-15 18:22:41 +0000510
511#define SECTORSIZE 512
512#define ADDR_COLUMN 1
513#define ADDR_PAGE 2
514#define ADDR_COLUMN_PAGE 3
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200515#define NAND_ChipID_UNKNOWN 0x00
wdenk04a85b32004-04-15 18:22:41 +0000516#define NAND_MAX_FLOORS 1
wdenk04a85b32004-04-15 18:22:41 +0000517
518/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
519#define NAND_DISABLE_CE(nand) \
520 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
wdenk04a85b32004-04-15 18:22:41 +0000522 } while(0)
523
524#define NAND_ENABLE_CE(nand) \
525 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
wdenk04a85b32004-04-15 18:22:41 +0000527 } while(0)
528
529#define NAND_CTL_CLRALE(nandptr) \
530 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200531 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
wdenk04a85b32004-04-15 18:22:41 +0000532 } while(0)
533
534#define NAND_CTL_SETALE(nandptr) \
535 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
wdenk04a85b32004-04-15 18:22:41 +0000537 } while(0)
538
539#define NAND_CTL_CLRCLE(nandptr) \
540 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
wdenk04a85b32004-04-15 18:22:41 +0000542 } while(0)
543
544#define NAND_CTL_SETCLE(nandptr) \
545 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
wdenk04a85b32004-04-15 18:22:41 +0000547 } while(0)
548
wdenkc26e4542004-04-18 10:13:26 +0000549#if CONFIG_NETPHONE_VERSION == 1
wdenk04a85b32004-04-15 18:22:41 +0000550#define NAND_WAIT_READY(nand) \
551 do { \
wdenkc26e4542004-04-18 10:13:26 +0000552 int _tries = 0; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
wdenkc26e4542004-04-18 10:13:26 +0000554 if (++_tries > 100000) \
555 break; \
wdenk04a85b32004-04-15 18:22:41 +0000556 } while (0)
wdenkc26e4542004-04-18 10:13:26 +0000557#elif CONFIG_NETPHONE_VERSION == 2
558#define NAND_WAIT_READY(nand) \
559 do { \
560 int _tries = 0; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
wdenkc26e4542004-04-18 10:13:26 +0000562 if (++_tries > 100000) \
563 break; \
564 } while (0)
565#endif
wdenk04a85b32004-04-15 18:22:41 +0000566
567#define WRITE_NAND_COMMAND(d, adr) \
568 do { \
569 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
570 } while(0)
571
572#define WRITE_NAND_ADDRESS(d, adr) \
573 do { \
574 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
575 } while(0)
576
577#define WRITE_NAND(d, adr) \
578 do { \
579 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
580 } while(0)
581
582#define READ_NAND(adr) \
583 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
584
585/*****************************************************************************/
586
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200587#define CONFIG_SYS_DIRECT_FLASH_TFTP
588#define CONFIG_SYS_DIRECT_NAND_TFTP
wdenk79fa88f2004-06-07 23:46:25 +0000589
590/*****************************************************************************/
591
wdenkc26e4542004-04-18 10:13:26 +0000592#if CONFIG_NETPHONE_VERSION == 1
wdenk04a85b32004-04-15 18:22:41 +0000593#define STATUS_LED_BIT 0x00000008 /* bit 28 */
wdenkc26e4542004-04-18 10:13:26 +0000594#elif CONFIG_NETPHONE_VERSION == 2
595#define STATUS_LED_BIT 0x00000080 /* bit 24 */
596#endif
597
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200598#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
wdenk04a85b32004-04-15 18:22:41 +0000599#define STATUS_LED_STATE STATUS_LED_BLINKING
600
601#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
602#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
603
604#ifndef __ASSEMBLY__
605
606/* LEDs */
607
608/* led_id_t is unsigned int mask */
609typedef unsigned int led_id_t;
610
611#define __led_toggle(_msk) \
612 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200613 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
wdenk04a85b32004-04-15 18:22:41 +0000614 } while(0)
615
616#define __led_set(_msk, _st) \
617 do { \
618 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
wdenk04a85b32004-04-15 18:22:41 +0000620 else \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200621 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
wdenk04a85b32004-04-15 18:22:41 +0000622 } while(0)
623
624#define __led_init(msk, st) __led_set(msk, st)
625
626#endif
627
628/***********************************************************************************************************
629
wdenkc26e4542004-04-18 10:13:26 +0000630 ----------------------------------------------------------------------------------------------
631
632 (V1) version 1 of the board
633 (V2) version 2 of the board
634
635 ----------------------------------------------------------------------------------------------
636
wdenk04a85b32004-04-15 18:22:41 +0000637 Pin definitions:
638
639 +------+----------------+--------+------------------------------------------------------------
640 | # | Name | Type | Comment
641 +------+----------------+--------+------------------------------------------------------------
642 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
643 | PA7 | DSP_INT | Output | DSP interrupt
644 | PA10 | DSP_RESET | Output | DSP reset
645 | PA14 | USBOE | Output | USB (1)
646 | PA15 | USBRXD | Output | USB (1)
647 | PB19 | BT_RTS | Output | Bluetooth (0)
648 | PB23 | BT_CTS | Output | Bluetooth (0)
649 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
650 | PB27 | SPICS_DISP | Output | Display chip select
651 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
652 | PB29 | SPI_TXD | Output | SPI Data Tx
653 | PB30 | SPI_CLK | Output | SPI Clock
654 | PC10 | DISPA0 | Output | Display A0
655 | PC11 | BACKLIGHT | Output | Display backlit
wdenkc26e4542004-04-18 10:13:26 +0000656 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
657 | | IO_RESET | Output | (V2) General I/O reset
658 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
659 | | HOOK | Input | (V2) Hook input interrupt
660 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
661 | | F_RY_BY | Input | (V2) NAND F_RY_BY
wdenk04a85b32004-04-15 18:22:41 +0000662 | PE17 | F_ALE | Output | NAND F_ALE
663 | PE18 | F_CLE | Output | NAND F_CLE
664 | PE20 | F_CE | Output | NAND F_CE
wdenkc26e4542004-04-18 10:13:26 +0000665 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
666 | | LED | Output | (V2) LED
wdenk04a85b32004-04-15 18:22:41 +0000667 | PE27 | SPICS_ER | Output | External serial register CS
wdenkc26e4542004-04-18 10:13:26 +0000668 | PE28 | LEDIO1 | Output | (V1) LED
669 | | BKBR1 | Input | (V2) Keyboard input scan
670 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
671 | | BKBR2 | Input | (V2) Keyboard input scan
672 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
673 | | BKBR3 | Input | (V2) Keyboard input scan
674 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
675 | | BKBR4 | Input | (V2) Keyboard input scan
wdenk04a85b32004-04-15 18:22:41 +0000676 +------+----------------+--------+---------------------------------------------------
677
wdenkc26e4542004-04-18 10:13:26 +0000678 ----------------------------------------------------------------------------------------------
679
680 Serial register input:
681
682 +------+----------------+------------------------------------------------------------
683 | # | Name | Comment
684 +------+----------------+------------------------------------------------------------
wdenk6e592382004-04-18 17:39:38 +0000685 | 0 | BKBR1 | (V1) Keyboard input scan
686 | 1 | BKBR3 | (V1) Keyboard input scan
687 | 2 | BKBR4 | (V1) Keyboard input scan
688 | 3 | BKBR2 | (V1) Keyboard input scan
689 | 4 | HOOK | (V1) Hook switch
wdenkc26e4542004-04-18 10:13:26 +0000690 | 5 | BT_LINK | (V1) Bluetooth link status
691 | 6 | HOST_WAKE | (V1) Bluetooth host wake up
692 | 7 | OK_ETH | (V1) Cisco inline power OK status
693 +------+----------------+------------------------------------------------------------
694
695 ----------------------------------------------------------------------------------------------
696
697 Serial register output:
698
699 +------+----------------+------------------------------------------------------------
700 | # | Name | Comment
701 +------+----------------+------------------------------------------------------------
wdenk6e592382004-04-18 17:39:38 +0000702 | 0 | KEY1 | Keyboard output scan
703 | 1 | KEY2 | Keyboard output scan
704 | 2 | KEY3 | Keyboard output scan
705 | 3 | KEY4 | Keyboard output scan
706 | 4 | KEY5 | Keyboard output scan
707 | 5 | KEY6 | Keyboard output scan
708 | 6 | KEY7 | Keyboard output scan
wdenkc26e4542004-04-18 10:13:26 +0000709 | 7 | BT_WAKE | Bluetooth wake up
710 +------+----------------+------------------------------------------------------------
711
712 ----------------------------------------------------------------------------------------------
713
wdenk04a85b32004-04-15 18:22:41 +0000714 Chip selects:
715
716 +------+----------------+------------------------------------------------------------
717 | # | Name | Comment
718 +------+----------------+------------------------------------------------------------
719 | CS0 | CS0 | Boot flash
720 | CS1 | CS_FLASH | NAND flash
721 | CS2 | CS_DSP | DSP
722 | CS3 | DCS_DRAM | DRAM
wdenkc26e4542004-04-18 10:13:26 +0000723 | CS4 | CS_FLASH2 | (V2) 2nd flash
wdenk04a85b32004-04-15 18:22:41 +0000724 +------+----------------+------------------------------------------------------------
725
wdenkc26e4542004-04-18 10:13:26 +0000726 ----------------------------------------------------------------------------------------------
727
wdenk04a85b32004-04-15 18:22:41 +0000728 Interrupts:
729
730 +------+----------------+------------------------------------------------------------
731 | # | Name | Comment
732 +------+----------------+------------------------------------------------------------
733 | IRQ1 | IRQ_DSP | DSP interrupt
734 | IRQ3 | S_INTER | DUSLIC ???
735 | IRQ4 | F_RY_BY | NAND
736 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
737 +------+----------------+------------------------------------------------------------
738
wdenkc26e4542004-04-18 10:13:26 +0000739 ----------------------------------------------------------------------------------------------
740
wdenk04a85b32004-04-15 18:22:41 +0000741 Interrupts on PCMCIA pins:
742
743 +------+----------------+------------------------------------------------------------
744 | # | Name | Comment
745 +------+----------------+------------------------------------------------------------
746 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
747 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
748 | IP_A2| RMII1_MDINT | PHY interrupt for #1
749 | IP_A3| RMII2_MDINT | PHY interrupt for #2
wdenkc26e4542004-04-18 10:13:26 +0000750 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
751 | IP_A6| OK_ETH | (V2) Cisco inline power OK
wdenk04a85b32004-04-15 18:22:41 +0000752 +------+----------------+------------------------------------------------------------
753
754*************************************************************************************************/
755
756#define CONFIG_SED156X 1 /* use SED156X */
757#define CONFIG_SED156X_PG12864Q 1 /* type of display used */
758
759/* serial interfacing macros */
760
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200761#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
wdenk04a85b32004-04-15 18:22:41 +0000762#define SED156X_SPI_RXD_MASK 0x00000008
763
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200764#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
wdenk04a85b32004-04-15 18:22:41 +0000765#define SED156X_SPI_TXD_MASK 0x00000004
766
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200767#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
wdenk04a85b32004-04-15 18:22:41 +0000768#define SED156X_SPI_CLK_MASK 0x00000002
769
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200770#define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
wdenk04a85b32004-04-15 18:22:41 +0000771#define SED156X_CS_MASK 0x00000010
772
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200773#define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
wdenk04a85b32004-04-15 18:22:41 +0000774#define SED156X_A0_MASK 0x0020
775
776/*************************************************************************************************/
777
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200778#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
779#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
780#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
wdenk04a85b32004-04-15 18:22:41 +0000781
782/*************************************************************************************************/
783
784/* use board specific hardware */
785#undef CONFIG_WATCHDOG /* watchdog disabled */
786#define CONFIG_HW_WATCHDOG
787#define CONFIG_SHOW_ACTIVITY
788
789/*************************************************************************************************/
790
791/* phone console configuration */
792
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200793#define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */
wdenk04a85b32004-04-15 18:22:41 +0000794
795/*************************************************************************************************/
796
797#define CONFIG_CDP_DEVICE_ID 20
798#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */
799#define CONFIG_CDP_PORT_ID "eth%d"
800#define CONFIG_CDP_CAPABILITIES 0x00000010
Peter Tyser561858e2008-11-03 09:30:59 -0600801#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
wdenk04a85b32004-04-15 18:22:41 +0000802#define CONFIG_CDP_PLATFORM "Intracom NetPhone"
803#define CONFIG_CDP_TRIGGER 0x20020001
804#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
805#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */
806
807/*************************************************************************************************/
808
809#define CONFIG_AUTO_COMPLETE 1
810
811/*************************************************************************************************/
812
wdenkc26e4542004-04-18 10:13:26 +0000813#define CONFIG_CRC32_VERIFY 1
814
815/*************************************************************************************************/
816
817#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
818
819/*************************************************************************************************/
wdenk04a85b32004-04-15 18:22:41 +0000820#endif /* __CONFIG_H */