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gerrit.cesnet.cz / github / trini / u-boot / 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73 / . / include / asm-m68k / immap_5272.h
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wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * MCF5272 Internal Memory Map
3 *
4 * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __IMMAP_5272__
26#define __IMMAP_5272__
27
28/* System configuration registers
29*/
30typedef struct sys_ctrl {
31 uint sc_mbar;
32 ushort sc_scr;
33 ushort sc_spr;
34 uint sc_pmr;
35 char res1[2];
36 ushort sc_alpr;
37 uint sc_dir;
38 char res2[12];
39} sysctrl_t;
40
41/* Interrupt module registers
42*/
43typedef struct int_ctrl {
44 uint int_icr1;
45 uint int_icr2;
46 uint int_icr3;
47 uint int_icr4;
48 uint int_isr;
49 uint int_pitr;
50 uint int_piwr;
51 uchar res1[3];
52 uchar int_pivr;
53} intctrl_t;
54
55/* Chip select module registers.
56*/
57typedef struct cs_ctlr {
58 uint cs_br0;
59 uint cs_or0;
60 uint cs_br1;
61 uint cs_or1;
62 uint cs_br2;
63 uint cs_or2;
64 uint cs_br3;
65 uint cs_or3;
66 uint cs_br4;
67 uint cs_or4;
68 uint cs_br5;
69 uint cs_or5;
70 uint cs_br6;
71 uint cs_or6;
72 uint cs_br7;
73 uint cs_or7;
74} csctrl_t;
75
76/* GPIO port registers
77*/
78typedef struct gpio_ctrl {
79 uint gpio_pacnt;
80 ushort gpio_paddr;
81 ushort gpio_padat;
82 uint gpio_pbcnt;
83 ushort gpio_pbddr;
84 ushort gpio_pbdat;
85 uchar res1[4];
86 ushort gpio_pcddr;
87 ushort gpio_pcdat;
88 uint gpio_pdcnt;
89 uchar res2[4];
90} gpio_t;
91
92/* QSPI module registers
93 */
94typedef struct qspi_ctrl {
95 ushort qspi_qmr;
96 uchar res1[2];
97 ushort qspi_qdlyr;
98 uchar res2[2];
99 ushort qspi_qwr;
100 uchar res3[2];
101 ushort qspi_qir;
102 uchar res4[2];
103 ushort qspi_qar;
104 uchar res5[2];
105 ushort qspi_qdr;
106 uchar res6[10];
107} qspi_t;
108
109/* PWM module registers
110 */
111typedef struct pwm_ctrl {
112 uchar pwm_pwcr0;
113 uchar res1[3];
114 uchar pwm_pwcr1;
115 uchar res2[3];
116 uchar pwm_pwcr2;
117 uchar res3[7];
118 uchar pwm_pwwd0;
119 uchar res4[3];
120 uchar pwm_pwwd1;
121 uchar res5[3];
122 uchar pwm_pwwd2;
123 uchar res6[7];
124} pwm_t;
125
126/* DMA module registers
127 */
128typedef struct dma_ctrl {
129 ulong dma_dmr;
130 uchar res1[2];
131 ushort dma_dir;
132 ulong dma_dbcr;
133 ulong dma_dsar;
134 ulong dma_ddar;
135 uchar res2[12];
136} dma_t;
137
138/* UART module registers
139 */
140typedef struct uart_ctrl {
141 uchar uart_umr;
142 uchar res1[3];
143 uchar uart_usr_ucsr;
144 uchar res2[3];
145 uchar uart_ucr;
146 uchar res3[3];
147 uchar uart_urb_utb;
148 uchar res4[3];
149 uchar uart_uipcr_uacr;
150 uchar res5[3];
151 uchar uart_uisr_uimr;
152 uchar res6[3];
153 uchar uart_udu;
154 uchar res7[3];
155 uchar uart_udl;
156 uchar res8[3];
157 uchar uart_uabu;
158 uchar res9[3];
159 uchar uart_uabl;
160 uchar res10[3];
161 uchar uart_utf;
162 uchar res11[3];
163 uchar uart_urf;
164 uchar res12[3];
165 uchar uart_ufpd;
166 uchar res13[3];
167 uchar uart_uip;
168 uchar res14[3];
169 uchar uart_uop1;
170 uchar res15[3];
171 uchar uart_uop0;
172 uchar res16[3];
173} uart_t;
174
175/* SDRAM controller registers, offset: 0x180
176 */
177typedef struct sdram_ctrl {
178 uchar res1[2];
179 ushort sdram_sdcr;
180 uchar res2[2];
181 ushort sdram_sdtr;
182 uchar res3[120];
183} sdramctrl_t;
184
185/* Timer module registers
186 */
187typedef struct timer_ctrl {
188 ushort timer_tmr;
189 ushort res1;
190 ushort timer_trr;
191 ushort res2;
192 ushort timer_tcap;
193 ushort res3;
194 ushort timer_tcn;
195 ushort res4;
196 ushort timer_ter;
197 uchar res5[14];
198} timer_t;
199
200/* Watchdog registers
201 */
202typedef struct wdog_ctrl {
203 ushort wdog_wrrr;
204 ushort res1;
205 ushort wdog_wirr;
206 ushort res2;
207 ushort wdog_wcr;
208 ushort res3;
209 ushort wdog_wer;
210 uchar res4[114];
211} wdog_t;
212
213/* PLIC module registers
214 */
215typedef struct plic_ctrl {
216 ulong plic_p0b1rr;
217 ulong plic_p1b1rr;
218 ulong plic_p2b1rr;
219 ulong plic_p3b1rr;
220 ulong plic_p0b2rr;
221 ulong plic_p1b2rr;
222 ulong plic_p2b2rr;
223 ulong plic_p3b2rr;
224 uchar plic_p0drr;
225 uchar plic_p1drr;
226 uchar plic_p2drr;
227 uchar plic_p3drr;
228 uchar res1[4];
229 ulong plic_p0b1tr;
230 ulong plic_p1b1tr;
231 ulong plic_p2b1tr;
232 ulong plic_p3b1tr;
233 ulong plic_p0b2tr;
234 ulong plic_p1b2tr;
235 ulong plic_p2b2tr;
236 ulong plic_p3b2tr;
237 uchar plic_p0dtr;
238 uchar plic_p1dtr;
239 uchar plic_p2dtr;
240 uchar plic_p3dtr;
241 uchar res2[4];
242 ushort plic_p0cr;
243 ushort plic_p1cr;
244 ushort plic_p2cr;
245 ushort plic_p3cr;
246 ushort plic_p0icr;
247 ushort plic_p1icr;
248 ushort plic_p2icr;
249 ushort plic_p3icr;
250 ushort plic_p0gmr;
251 ushort plic_p1gmr;
252 ushort plic_p2gmr;
253 ushort plic_p3gmr;
254 ushort plic_p0gmt;
255 ushort plic_p1gmt;
256 ushort plic_p2gmt;
257 ushort plic_p3gmt;
258 uchar res3;
259 uchar plic_pgmts;
260 uchar plic_pgmta;
261 uchar res4;
262 uchar plic_p0gcir;
263 uchar plic_p1gcir;
264 uchar plic_p2gcir;
265 uchar plic_p3gcir;
266 uchar plic_p0gcit;
267 uchar plic_p1gcit;
268 uchar plic_p2gcit;
269 uchar plic_p3gcit;
270 uchar res5[3];
271 uchar plic_pgcitsr;
272 uchar res6[3];
273 uchar plic_pdcsr;
274 ushort plic_p0psr;
275 ushort plic_p1psr;
276 ushort plic_p2psr;
277 ushort plic_p3psr;
278 ushort plic_pasr;
279 uchar res7;
280 uchar plic_plcr;
281 ushort res8;
282 ushort plic_pdrqr;
283 ushort plic_p0sdr;
284 ushort plic_p1sdr;
285 ushort plic_p2sdr;
286 ushort plic_p3sdr;
287 ushort res9;
288 ushort plic_pcsr;
289 uchar res10[1184];
290} plic_t;
291
292/* Fast ethernet controller registers
293 */
294typedef struct fec {
295 uint fec_ecntrl; /* ethernet control register */
296 uint fec_ievent; /* interrupt event register */
297 uint fec_imask; /* interrupt mask register */
298 uint fec_ivec; /* interrupt level and vector status */
299 uint fec_r_des_active; /* Rx ring updated flag */
300 uint fec_x_des_active; /* Tx ring updated flag */
301 uint res3[10]; /* reserved */
302 uint fec_mii_data; /* MII data register */
303 uint fec_mii_speed; /* MII speed control register */
304 uint res4[17]; /* reserved */
305 uint fec_r_bound; /* end of RAM (read-only) */
306 uint fec_r_fstart; /* Rx FIFO start address */
307 uint res5[6]; /* reserved */
308 uint fec_x_fstart; /* Tx FIFO start address */
309 uint res7[21]; /* reserved */
310 uint fec_r_cntrl; /* Rx control register */
311 uint fec_r_hash; /* Rx hash register */
312 uint res8[14]; /* reserved */
313 uint fec_x_cntrl; /* Tx control register */
314 uint res9[0x9e]; /* reserved */
315 uint fec_addr_low; /* lower 32 bits of station address */
316 uint fec_addr_high; /* upper 16 bits of station address */
317 uint fec_hash_table_high; /* upper 32-bits of hash table */
318 uint fec_hash_table_low; /* lower 32-bits of hash table */
319 uint fec_r_des_start; /* beginning of Rx descriptor ring */
320 uint fec_x_des_start; /* beginning of Tx descriptor ring */
321 uint fec_r_buff_size; /* Rx buffer size */
322 uint res2[9]; /* reserved */
323 uchar fec_fifo[960]; /* fifo RAM */
324} fec_t;
325
326/* USB module registers
327*/
328typedef struct usb {
329 ushort res1;
330 ushort usb_fnr;
331 ushort res2;
332 ushort usb_fnmr;
333 ushort res3;
334 ushort usb_rfmr;
335 ushort res4;
336 ushort usb_rfmmr;
337 uchar res5[3];
338 uchar usb_far;
339 ulong usb_asr;
340 ulong usb_drr1;
341 ulong usb_drr2;
342 ushort res6;
343 ushort usb_specr;
344 ushort res7;
345 ushort usb_ep0sr;
346 ulong usb_iep0cfg;
347 ulong usb_oep0cfg;
348 ulong usb_ep1cfg;
349 ulong usb_ep2cfg;
350 ulong usb_ep3cfg;
351 ulong usb_ep4cfg;
352 ulong usb_ep5cfg;
353 ulong usb_ep6cfg;
354 ulong usb_ep7cfg;
355 ulong usb_ep0ctl;
356 ushort res8;
357 ushort usb_ep1ctl;
358 ushort res9;
359 ushort usb_ep2ctl;
360 ushort res10;
361 ushort usb_ep3ctl;
362 ushort res11;
363 ushort usb_ep4ctl;
364 ushort res12;
365 ushort usb_ep5ctl;
366 ushort res13;
367 ushort usb_ep6ctl;
368 ushort res14;
369 ushort usb_ep7ctl;
370 ulong usb_ep0isr;
371 ushort res15;
372 ushort usb_ep1isr;
373 ushort res16;
374 ushort usb_ep2isr;
375 ushort res17;
376 ushort usb_ep3isr;
377 ushort res18;
378 ushort usb_ep4isr;
379 ushort res19;
380 ushort usb_ep5isr;
381 ushort res20;
382 ushort usb_ep6isr;
383 ushort res21;
384 ushort usb_ep7isr;
385 ulong usb_ep0imr;
386 ushort res22;
387 ushort usb_ep1imr;
388 ushort res23;
389 ushort usb_ep2imr;
390 ushort res24;
391 ushort usb_ep3imr;
392 ushort res25;
393 ushort usb_ep4imr;
394 ushort res26;
395 ushort usb_ep5imr;
396 ushort res27;
397 ushort usb_ep6imr;
398 ushort res28;
399 ushort usb_ep7imr;
400 ulong usb_ep0dr;
401 ulong usb_ep1dr;
402 ulong usb_ep2dr;
403 ulong usb_ep3dr;
404 ulong usb_ep4dr;
405 ulong usb_ep5dr;
406 ulong usb_ep6dr;
407 ulong usb_ep7dr;
408 ushort res29;
409 ushort usb_ep0dpr;
410 ushort res30;
411 ushort usb_ep1dpr;
412 ushort res31;
413 ushort usb_ep2dpr;
414 ushort res32;
415 ushort usb_ep3dpr;
416 ushort res33;
417 ushort usb_ep4dpr;
418 ushort res34;
419 ushort usb_ep5dpr;
420 ushort res35;
421 ushort usb_ep6dpr;
422 ushort res36;
423 ushort usb_ep7dpr;
424 uchar res37[788];
425 uchar usb_cfgram[1024];
426} usb_t;
427
428/* Internal memory map.
429*/
430typedef struct immap {
431 sysctrl_t sysctrl_reg; /* System configuration registers */
432 intctrl_t intctrl_reg; /* Interrupt controller registers */
433 csctrl_t csctrl_reg; /* Chip select controller registers */
434 gpio_t gpio_reg; /* GPIO controller registers */
435 qspi_t qspi_reg; /* QSPI controller registers */
436 pwm_t pwm_reg; /* Pulse width modulation registers */
437 dma_t dma_reg; /* DMA registers */
438 uart_t uart_reg[2]; /* UART registers */
439 sdramctrl_t sdram_reg; /* SDRAM controller registers */
440 timer_t timer_reg[4]; /* Timer registers */
441 wdog_t wdog_reg; /* Watchdog registers */
442 plic_t plic_reg; /* Physical layer interface registers */
443 fec_t fec_reg; /* Fast ethernet controller registers */
444 usb_t usb_reg; /* USB controller registers */
445} immap_t;
446
447#endif /* __IMMAP_5272__ */