blob: c2f6e2848ef1db7750ba03edfb41de2ae55f9adf [file] [log] [blame]
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01001/*
2 * U-boot - cache.c
3 *
Mike Frysingerb86b3412008-02-19 00:50:58 -05004 * Copyright (c) 2005-2008 Analog Devices Inc.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
Mike Frysingerb86b3412008-02-19 00:50:58 -05009 * Licensed under the GPL-2 or later.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010010 */
11
Aubrey.Li3f0606a2007-03-09 13:38:44 +080012#include <common.h>
13#include <asm/blackfin.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +080014
Mike Frysingerb86b3412008-02-19 00:50:58 -050015void flush_cache(unsigned long addr, unsigned long size)
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010016{
Mike Frysingerb86b3412008-02-19 00:50:58 -050017 /* no need to flush stuff in on chip memory (L1/L2/etc...) */
18 if (addr >= 0xE0000000)
Aubrey.Li3f0606a2007-03-09 13:38:44 +080019 return;
20
21 if (icache_status())
Mike Frysingerb86b3412008-02-19 00:50:58 -050022 blackfin_icache_flush_range((void *)addr, (void *)(addr + size));
Aubrey.Li3f0606a2007-03-09 13:38:44 +080023
Mike Frysingerb86b3412008-02-19 00:50:58 -050024 if (dcache_status())
25 blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010026}