wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 1 | /*----------------------------------------------------------------------------+ |
Josh Boyer | 3177349 | 2009-08-07 13:53:20 -0400 | [diff] [blame] | 2 | | This source code is dual-licensed. You may use it under the terms of |
| 3 | | the GNU General Public License version 2, or under the license below. |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 4 | | |
| 5 | | This source code has been made available to you by IBM on an AS-IS |
| 6 | | basis. Anyone receiving this source is licensed under IBM |
| 7 | | copyrights to use it in any way he or she deems fit, including |
| 8 | | copying it, modifying it, compiling it, and redistributing it either |
| 9 | | with or without modifications. No license under IBM patents or |
| 10 | | patent applications is to be implied by the copyright license. |
| 11 | | |
| 12 | | Any user of this software should understand that IBM cannot provide |
| 13 | | technical support for this software and will not be responsible for |
| 14 | | any consequences resulting from the use of this software. |
| 15 | | |
| 16 | | Any person who transfers this source code or any derivative work |
| 17 | | must include the IBM copyright notice, this paragraph, and the |
| 18 | | preceding two paragraphs in the transferred software. |
| 19 | | |
| 20 | | COPYRIGHT I B M CORPORATION 1999 |
| 21 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
| 22 | +----------------------------------------------------------------------------*/ |
| 23 | |
| 24 | #ifndef __PPC4XX_H__ |
| 25 | #define __PPC4XX_H__ |
| 26 | |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 27 | /* |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 28 | * Include SoC specific headers |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 29 | */ |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 30 | #if defined(CONFIG_405CR) |
| 31 | #include <asm/ppc405cr.h> |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 32 | #endif |
| 33 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 34 | #if defined(CONFIG_405EP) |
| 35 | #include <asm/ppc405ep.h> |
| 36 | #endif |
| 37 | |
| 38 | #if defined(CONFIG_405EX) |
| 39 | #include <asm/ppc405ex.h> |
| 40 | #endif |
| 41 | |
| 42 | #if defined(CONFIG_405EZ) |
| 43 | #include <asm/ppc405ez.h> |
| 44 | #endif |
| 45 | |
| 46 | #if defined(CONFIG_405GP) |
| 47 | #include <asm/ppc405gp.h> |
| 48 | #endif |
| 49 | |
| 50 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
| 51 | #include <asm/ppc440ep_gr.h> |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 52 | #endif |
| 53 | |
| 54 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 55 | #include <asm/ppc440epx_grx.h> |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 56 | #endif |
| 57 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 58 | #if defined(CONFIG_440GP) |
| 59 | #include <asm/ppc440gp.h> |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 60 | #endif |
| 61 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 62 | #if defined(CONFIG_440GX) |
| 63 | #include <asm/ppc440gx.h> |
Stefan Roese | 5d841fa | 2009-05-20 10:58:01 +0200 | [diff] [blame] | 64 | #endif |
| 65 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 66 | #if defined(CONFIG_440SP) |
| 67 | #include <asm/ppc440sp.h> |
| 68 | #endif |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 69 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 70 | #if defined(CONFIG_440SPE) |
| 71 | #include <asm/ppc440spe.h> |
| 72 | #endif |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 73 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 74 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 75 | #include <asm/ppc460ex_gt.h> |
| 76 | #endif |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 77 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 78 | #if defined(CONFIG_460SX) |
| 79 | #include <asm/ppc460sx.h> |
| 80 | #endif |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 81 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame^] | 82 | /* |
| 83 | * Configure which SDRAM/DDR/DDR2 controller is equipped |
| 84 | */ |
| 85 | // test-only: what to do with these??? |
| 86 | #if defined(CONFIG_AP1000) || defined(CONFIG_ML2) |
| 87 | #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ |
| 88 | #endif |
| 89 | |
| 90 | /* |
| 91 | * Common registers for all SoC's |
| 92 | */ |
| 93 | /* DCR registers */ |
| 94 | #define PLB3A0_ACR 0x0077 |
| 95 | #define PLB4A0_ACR 0x0081 |
| 96 | #define PLB4A1_ACR 0x0089 |
| 97 | |
| 98 | #define PLB4Ax_ACR_PPM_MASK 0xf0000000 |
| 99 | #define PLB4Ax_ACR_PPM_FIXED 0x00000000 |
| 100 | #define PLB4Ax_ACR_PPM_FAIR 0xd0000000 |
| 101 | #define PLB4Ax_ACR_HBU_MASK 0x08000000 |
| 102 | #define PLB4Ax_ACR_HBU_DISABLED 0x00000000 |
| 103 | #define PLB4Ax_ACR_HBU_ENABLED 0x08000000 |
| 104 | #define PLB4Ax_ACR_RDP_MASK 0x06000000 |
| 105 | #define PLB4Ax_ACR_RDP_DISABLED 0x00000000 |
| 106 | #define PLB4Ax_ACR_RDP_2DEEP 0x02000000 |
| 107 | #define PLB4Ax_ACR_RDP_3DEEP 0x04000000 |
| 108 | #define PLB4Ax_ACR_RDP_4DEEP 0x06000000 |
| 109 | #define PLB4Ax_ACR_WRP_MASK 0x01000000 |
| 110 | #define PLB4Ax_ACR_WRP_DISABLED 0x00000000 |
| 111 | #define PLB4Ax_ACR_WRP_2DEEP 0x01000000 |
| 112 | |
| 113 | /* General Purpose Timer (GPT) Register Offsets */ |
| 114 | #define GPT0_TBC 0x00000000 |
| 115 | #define GPT0_IM 0x00000018 |
| 116 | #define GPT0_ISS 0x0000001C |
| 117 | #define GPT0_ISC 0x00000020 |
| 118 | #define GPT0_IE 0x00000024 |
| 119 | #define GPT0_COMP0 0x00000080 |
| 120 | #define GPT0_COMP1 0x00000084 |
| 121 | #define GPT0_COMP2 0x00000088 |
| 122 | #define GPT0_COMP3 0x0000008C |
| 123 | #define GPT0_COMP4 0x00000090 |
| 124 | #define GPT0_COMP5 0x00000094 |
| 125 | #define GPT0_COMP6 0x00000098 |
| 126 | #define GPT0_MASK0 0x000000C0 |
| 127 | #define GPT0_MASK1 0x000000C4 |
| 128 | #define GPT0_MASK2 0x000000C8 |
| 129 | #define GPT0_MASK3 0x000000CC |
| 130 | #define GPT0_MASK4 0x000000D0 |
| 131 | #define GPT0_MASK5 0x000000D4 |
| 132 | #define GPT0_MASK6 0x000000D8 |
| 133 | #define GPT0_DCT0 0x00000110 |
| 134 | #define GPT0_DCIS 0x0000011C |
Prodyut Hazarika | 079589b | 2008-08-20 09:38:51 -0700 | [diff] [blame] | 135 | |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 136 | #if defined(CONFIG_440) |
Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 137 | #include <asm/ppc440.h> |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 138 | #else |
Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 139 | #include <asm/ppc405.h> |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 140 | #endif |
| 141 | |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 142 | #include <asm/ppc4xx-sdram.h> |
Stefan Roese | 7ee2619 | 2008-06-24 17:18:50 +0200 | [diff] [blame] | 143 | #include <asm/ppc4xx-ebc.h> |
Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 144 | #if !defined(CONFIG_XILINX_440) |
Stefan Roese | 4fb25a3 | 2008-06-25 10:59:22 +0200 | [diff] [blame] | 145 | #include <asm/ppc4xx-uic.h> |
Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 146 | #endif |
Stefan Roese | 36ea16f | 2008-06-02 14:57:41 +0200 | [diff] [blame] | 147 | |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 148 | /* |
Grant Erickson | c821b5f | 2008-05-22 14:44:14 -0700 | [diff] [blame] | 149 | * Macro for generating register field mnemonics |
| 150 | */ |
| 151 | #define PPC_REG_BITS 32 |
| 152 | #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) |
| 153 | |
| 154 | /* |
| 155 | * Elide casts when assembling register mnemonics |
| 156 | */ |
| 157 | #ifndef __ASSEMBLY__ |
| 158 | #define static_cast(type, val) (type)(val) |
| 159 | #else |
| 160 | #define static_cast(type, val) (val) |
| 161 | #endif |
| 162 | |
| 163 | /* |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 164 | * Common stuff for 4xx (405 and 440) |
| 165 | */ |
| 166 | |
Niklaus Giger | dbcc357 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 167 | #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 168 | #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) |
| 169 | |
| 170 | #define RESET_VECTOR 0xfffffffc |
Niklaus Giger | dbcc357 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 171 | #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for |
| 172 | cache line aligned data. */ |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 173 | |
| 174 | #define CPR0_DCR_BASE 0x0C |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 175 | #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) |
| 176 | #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 177 | |
| 178 | #define SDR_DCR_BASE 0x0E |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 179 | #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) |
| 180 | #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 181 | |
| 182 | #define SDRAM_DCR_BASE 0x10 |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 183 | #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) |
| 184 | #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 185 | |
| 186 | #define EBC_DCR_BASE 0x12 |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 187 | #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) |
| 188 | #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 189 | |
| 190 | /* |
| 191 | * Macros for indirect DCR access |
| 192 | */ |
Niklaus Giger | dbcc357 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 193 | #define mtcpr(reg, d) \ |
| 194 | do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0) |
| 195 | #define mfcpr(reg, d) \ |
| 196 | do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 197 | |
Niklaus Giger | dbcc357 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 198 | #define mtebc(reg, d) \ |
| 199 | do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0) |
| 200 | #define mfebc(reg, d) \ |
| 201 | do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 202 | |
Niklaus Giger | dbcc357 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 203 | #define mtsdram(reg, d) \ |
| 204 | do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0) |
| 205 | #define mfsdram(reg, d) \ |
| 206 | do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 207 | |
Niklaus Giger | dbcc357 | 2009-10-04 20:04:22 +0200 | [diff] [blame] | 208 | #define mtsdr(reg, d) \ |
| 209 | do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0) |
| 210 | #define mfsdr(reg, d) \ |
| 211 | do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0) |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 212 | |
| 213 | #ifndef __ASSEMBLY__ |
| 214 | |
| 215 | typedef struct |
| 216 | { |
| 217 | unsigned long freqDDR; |
| 218 | unsigned long freqEBC; |
| 219 | unsigned long freqOPB; |
| 220 | unsigned long freqPCI; |
| 221 | unsigned long freqPLB; |
| 222 | unsigned long freqTmrClk; |
| 223 | unsigned long freqUART; |
| 224 | unsigned long freqProcessor; |
| 225 | unsigned long freqVCOHz; |
| 226 | unsigned long freqVCOMhz; /* in MHz */ |
| 227 | unsigned long pciClkSync; /* PCI clock is synchronous */ |
| 228 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ |
| 229 | unsigned long pllExtBusDiv; |
| 230 | unsigned long pllFbkDiv; |
| 231 | unsigned long pllFwdDiv; |
| 232 | unsigned long pllFwdDivA; |
| 233 | unsigned long pllFwdDivB; |
| 234 | unsigned long pllOpbDiv; |
| 235 | unsigned long pllPciDiv; |
| 236 | unsigned long pllPlbDiv; |
| 237 | } PPC4xx_SYS_INFO; |
| 238 | |
Adam Graham | f6b6c45 | 2008-09-03 12:26:59 -0700 | [diff] [blame] | 239 | static inline u32 get_mcsr(void) |
| 240 | { |
| 241 | u32 val; |
| 242 | |
| 243 | asm volatile("mfspr %0, 0x23c" : "=r" (val) :); |
| 244 | return val; |
| 245 | } |
| 246 | |
| 247 | static inline void set_mcsr(u32 val) |
| 248 | { |
| 249 | asm volatile("mtspr 0x23c, %0" : "=r" (val) :); |
| 250 | } |
| 251 | |
Stefan Roese | 5e47f95 | 2009-10-19 14:06:23 +0200 | [diff] [blame] | 252 | int ppc4xx_pci_sync_clock_config(u32 async); |
| 253 | |
Stefan Roese | 087dfdb | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 254 | #endif /* __ASSEMBLY__ */ |
| 255 | |
Adam Graham | c9c11d7 | 2008-10-08 10:13:19 -0700 | [diff] [blame] | 256 | /* for multi-cpu support */ |
| 257 | #define NA_OR_UNKNOWN_CPU -1 |
| 258 | |
wdenk | 935ecca | 2002-08-06 20:46:37 +0000 | [diff] [blame] | 259 | #endif /* __PPC4XX_H__ */ |