blob: e03b1bcfaaa8b420371c7987b19db23b3430f26a [file] [log] [blame]
Lokesh Vutlafbf27282013-07-30 11:36:27 +05301/*
2 * mux.c
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/arch/mux.h>
Nishanth Menon5f8bb932016-02-24 12:30:56 -060012#include "../common/board_detect.h"
Lokesh Vutlafbf27282013-07-30 11:36:27 +053013#include "board.h"
14
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -050015static struct module_pin_mux rmii1_pin_mux[] = {
16 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
17 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
18 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
19 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
20 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
21 {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
22 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
23 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
24 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
25 {-1},
26};
27
28static struct module_pin_mux rgmii1_pin_mux[] = {
29 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
30 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
31 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
32 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
33 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
34 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
35 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
36 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
37 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
38 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
39 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
40 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
41 {-1},
42};
43
44static struct module_pin_mux mdio_pin_mux[] = {
45 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
46 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
47 {-1},
48};
49
Lokesh Vutlafbf27282013-07-30 11:36:27 +053050static struct module_pin_mux uart0_pin_mux[] = {
Lokesh Vutla48924952013-12-10 15:02:19 +053051 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
52 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
53 {-1},
54};
55
56static struct module_pin_mux mmc0_pin_mux[] = {
57 {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */
58 {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
59 {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
60 {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
61 {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
62 {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
63 {-1},
64};
65
66static struct module_pin_mux i2c0_pin_mux[] = {
67 {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
68 {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
Lokesh Vutlafbf27282013-07-30 11:36:27 +053069 {-1},
70};
71
Dave Gerlachcd8341b2014-02-10 11:41:49 -050072static struct module_pin_mux gpio5_7_pin_mux[] = {
73 {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +053074 {-1},
75};
76
pekon guptae53ad4b2014-07-22 16:03:22 +053077#ifdef CONFIG_NAND
78static struct module_pin_mux nand_pin_mux[] = {
79 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
80 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
81 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
82 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
83 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
84 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
85 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
86 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
87#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
88 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
89 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
90 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
91 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
92 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
93 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
94 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
95 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
96#endif
97 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
98 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
99 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
100 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
101 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
102 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
103 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
104 {-1},
105};
106#endif
107
108static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
Sourav Poddarea4c7a82013-12-21 12:50:08 +0530109 {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
110 {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
111 {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
112 {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
113 {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
114 {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
115 {-1},
116};
117
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530118void enable_uart0_pin_mux(void)
119{
120 configure_module_pin_mux(uart0_pin_mux);
121}
122
123void enable_board_pin_mux(void)
124{
Lokesh Vutla48924952013-12-10 15:02:19 +0530125 configure_module_pin_mux(mmc0_pin_mux);
126 configure_module_pin_mux(i2c0_pin_mux);
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500127 configure_module_pin_mux(mdio_pin_mux);
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530128
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500129 if (board_is_gpevm()) {
Dave Gerlachcd8341b2014-02-10 11:41:49 -0500130 configure_module_pin_mux(gpio5_7_pin_mux);
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500131 configure_module_pin_mux(rgmii1_pin_mux);
pekon guptae53ad4b2014-07-22 16:03:22 +0530132#if defined(CONFIG_NAND)
133 configure_module_pin_mux(nand_pin_mux);
134#endif
Felipe Balbi403d70a2014-12-22 16:26:17 -0600135 } else if (board_is_sk() || board_is_idk()) {
Felipe Balbi403edbb2014-06-10 15:01:22 -0500136 configure_module_pin_mux(rgmii1_pin_mux);
pekon guptae53ad4b2014-07-22 16:03:22 +0530137#if defined(CONFIG_NAND)
138 printf("Error: NAND flash not present on this board\n");
139#endif
Felipe Balbi403edbb2014-06-10 15:01:22 -0500140 configure_module_pin_mux(qspi_pin_mux);
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500141 } else if (board_is_eposevm()) {
142 configure_module_pin_mux(rmii1_pin_mux);
pekon guptae53ad4b2014-07-22 16:03:22 +0530143#if defined(CONFIG_NAND)
144 configure_module_pin_mux(nand_pin_mux);
145#else
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500146 configure_module_pin_mux(qspi_pin_mux);
pekon guptae53ad4b2014-07-22 16:03:22 +0530147#endif
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500148 }
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530149}
Lokesh Vutlacf04d032013-12-10 15:02:20 +0530150
151void enable_i2c0_pin_mux(void)
152{
153 configure_module_pin_mux(i2c0_pin_mux);
154}