blob: ddac6e44fd1b7ab9641e6b99d887698529a52593 [file] [log] [blame]
wdenk409bf352001-11-23 17:38:34 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * mpc75x.h
26 *
27 * MPC75x/MPC74xx specific definitions
28 */
29
30#ifndef __MPC75X_H__
31#define __MPC75X_H__
32
33/*----------------------------------------------------------------
34 * Exception offsets (PowerPC standard)
35 */
36#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
37
38/*----------------------------------------------------------------
39 * l2cr values
40 */
41#define l2cr 1017
42
43#define L2CR_L2E 0x80000000 /* bit 0 - enable */
44#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
45#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
46#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
47#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
48#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
49#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
50#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
51#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
52#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
53#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
54#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
55#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
56#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
57#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
58#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
59#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
60#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
61#define L2CR_TS 0x00040000 /* bit 13 - test support on */
62#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
63#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
64#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
65#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
66#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
67
68/*----------------------------------------------------------------
69 * BAT settings. Look in config_<BOARD>.h for the actual setup
70 */
71
72#define BATU_BL_128K 0x00000000
73#define BATU_BL_256K 0x00000004
74#define BATU_BL_512K 0x0000000c
75#define BATU_BL_1M 0x0000001c
76#define BATU_BL_2M 0x0000003c
77#define BATU_BL_4M 0x0000007c
78#define BATU_BL_8M 0x000000fc
79#define BATU_BL_16M 0x000001fc
80#define BATU_BL_32M 0x000003fc
81#define BATU_BL_64M 0x000007fc
82#define BATU_BL_128M 0x00000ffc
83#define BATU_BL_256M 0x00001ffc
84
85#define BATU_VS 0x00000002
86#define BATU_VP 0x00000001
87#define BATU_INVALID 0x00000000
88
89#define BATL_WRITETHROUGH 0x00000080
90#define BATL_CACHEINHIBIT 0x00000040
91#define BATL_COHERENT 0x00000020
92#define BATL_GUARDED 0x00000010
93
94#define BATL_NO_ACCESS 0x00000000
95#define BATL_RO 0x00000001
96#define BATL_RW 0x00000002
97
98#endif /* __MPC75X_H__ */