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gerrit.cesnet.cz / github / trini / u-boot / 5dc4538bf3fea0baf4ca2e4191e0e62991fbd779 / . / arch / arm / mach-uniphier / ph1-sld8 / pll_init.c
blob: 885100747dc1fce21961bf14e5eb192f616e45f1 [file] [log] [blame]
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]1/*
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
Masahiro Yamadaa86ac952015-02-27 02:26:44 +0900[diff] [blame]9#include <mach/sc-regs.h>
10#include <mach/sg-regs.h>
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]11
Masahiro Yamadaec79c792015-01-21 15:06:06 +0900[diff] [blame]12static void dpll_init(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]13{
14 u32 tmp;
15 /*
16 * Set DPLL SSC parameters for DPLLCTRL3
17 * [23] DIVN_TEST 0x1
18 * [22:16] DIVN 0x50
19 * [10] FREFSEL_TEST 0x1
20 * [9:8] FREFSEL 0x2
21 * [4] ICPD_TEST 0x1
22 * [3:0] ICPD 0xb
23 */
24 tmp = readl(SC_DPLLCTRL3);
25 tmp &= ~0x00ff0717;
26 tmp |= 0x00d0061b;
27 writel(tmp, SC_DPLLCTRL3);
28
29 /*
30 * Set DPLL SSC parameters for DPLLCTRL
31 * <-1%> <-2%>
32 * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
33 * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
34 */
35 tmp = readl(SC_DPLLCTRL);
36 tmp &= ~0x3ff07fff;
37#ifdef CONFIG_DPLL_SSC_RATE_1PER
38 tmp |= 0x084018bf;
39#else
40 tmp |= 0x084031a6;
41#endif
42 writel(tmp, SC_DPLLCTRL);
43
44 /*
45 * Set DPLL SSC parameters for DPLLCTRL2
46 * [31:29] SSC_STEP 0
47 * [27] SSC_REG_REF 1
48 * [26:20] SSC_M 79 (0x4f)
49 * [19:0] SSC_K 964689 (0xeb851)
50 */
51 tmp = readl(SC_DPLLCTRL2);
52 tmp &= ~0xefffffff;
53 tmp |= 0x0cfeb851;
54 writel(tmp, SC_DPLLCTRL2);
55}
56
Masahiro Yamadaec79c792015-01-21 15:06:06 +0900[diff] [blame]57static void upll_init(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]58{
59 u32 tmp, clk_mode_upll, clk_mode_axosel;
60
61 tmp = readl(SG_PINMON0);
62 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
63 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
64
65 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
66 tmp = readl(SC_UPLLCTRL);
67 tmp &= ~0x18000000;
68 writel(tmp, SC_UPLLCTRL);
69
70 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
71 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
72 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
73 /* AXO: 25MHz */
74 tmp &= ~0x07ffffff;
75 tmp |= 0x0228f5c0;
76 } else {
77 /* AXO: default 24.576MHz */
78 tmp &= ~0x07ffffff;
79 tmp |= 0x02328000;
80 }
81 }
82
83 writel(tmp, SC_UPLLCTRL);
84
85 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
86 tmp |= 0x08000000;
87 writel(tmp, SC_UPLLCTRL);
88
89 /* wait 10 usec */
90 udelay(10);
91
92 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
93 tmp |= 0x10000000;
94 writel(tmp, SC_UPLLCTRL);
95}
96
Masahiro Yamadaec79c792015-01-21 15:06:06 +0900[diff] [blame]97static void vpll_init(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]98{
99 u32 tmp, clk_mode_axosel;
100
101 tmp = readl(SG_PINMON0);
102 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
103
104 /* set 1 to VPLA27WP and VPLA27WP */
105 tmp = readl(SC_VPLL27ACTRL);
106 tmp |= 0x00000001;
107 writel(tmp, SC_VPLL27ACTRL);
108 tmp = readl(SC_VPLL27BCTRL);
109 tmp |= 0x00000001;
110 writel(tmp, SC_VPLL27BCTRL);
111
112 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
113 tmp = readl(SC_VPLL27ACTRL3);
114 tmp &= ~0x10000000;
115 writel(tmp, SC_VPLL27ACTRL3);
116 tmp = readl(SC_VPLL27BCTRL3);
117 tmp &= ~0x10000000;
118 writel(tmp, SC_VPLL27BCTRL3);
119
120 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
121 tmp = readl(SC_VPLL27ACTRL2);
122 tmp &= ~0x10000000;
123 writel(tmp, SC_VPLL27ACTRL2);
124 tmp = readl(SC_VPLL27BCTRL2);
125 tmp &= ~0x10000000;
126 writel(tmp, SC_VPLL27BCTRL2);
127
128 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
129 tmp = readl(SC_VPLL27ACTRL2);
130 tmp &= ~0x0000007f;
131 tmp |= 0x00000020;
132 writel(tmp, SC_VPLL27ACTRL2);
133 tmp = readl(SC_VPLL27BCTRL2);
134 tmp &= ~0x0000007f;
135 tmp |= 0x00000020;
136 writel(tmp, SC_VPLL27BCTRL2);
137
138 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
139 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
140 /* AXO: 25MHz */
141 tmp = readl(SC_VPLL27ACTRL3);
142 tmp &= ~0x000fffff;
143 tmp |= 0x00066664;
144 writel(tmp, SC_VPLL27ACTRL3);
145 tmp = readl(SC_VPLL27BCTRL3);
146 tmp &= ~0x000fffff;
147 tmp |= 0x00066664;
148 writel(tmp, SC_VPLL27BCTRL3);
149 } else {
150 /* AXO: default 24.576MHz */
151 tmp = readl(SC_VPLL27ACTRL3);
152 tmp &= ~0x000fffff;
153 tmp |= 0x000f5800;
154 writel(tmp, SC_VPLL27ACTRL3);
155 tmp = readl(SC_VPLL27BCTRL3);
156 tmp &= ~0x000fffff;
157 tmp |= 0x000f5800;
158 writel(tmp, SC_VPLL27BCTRL3);
159 }
160
161 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
162 tmp = readl(SC_VPLL27ACTRL3);
163 tmp |= 0x10000000;
164 writel(tmp, SC_VPLL27ACTRL3);
165 tmp = readl(SC_VPLL27BCTRL3);
166 tmp |= 0x10000000;
167 writel(tmp, SC_VPLL27BCTRL3);
168
169 /* wait 10 usec */
170 udelay(10);
171
172 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
173 tmp = readl(SC_VPLL27ACTRL2);
174 tmp |= 0x10000000;
175 writel(tmp, SC_VPLL27ACTRL2);
176 tmp = readl(SC_VPLL27BCTRL2);
177 tmp |= 0x10000000;
178 writel(tmp, SC_VPLL27BCTRL2);
179
180 /* set 0 to VPLA27WP and VPLA27WP */
181 tmp = readl(SC_VPLL27ACTRL);
182 tmp &= ~0x00000001;
183 writel(tmp, SC_VPLL27ACTRL);
184 tmp = readl(SC_VPLL27BCTRL);
185 tmp |= ~0x00000001;
186 writel(tmp, SC_VPLL27BCTRL);
187}
188
189void pll_init(void)
190{
191 dpll_init();
192 upll_init();
193 vpll_init();
194
195 /*
196 * Wait 500 usec until dpll get stable
197 * We wait 10 usec in upll_init() and vpll_init()
198 * so 20 usec can be saved here.
199 */
200 udelay(480);
201}