blob: bec092e4cebc64ff6d90ae6bbe2df3f8c044dee1 [file] [log] [blame]
wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26void flush_cache (ulong start_addr, ulong size)
27{
28 ulong addr, end_addr = start_addr + size;
29
30 if (CFG_CACHELINE_SIZE) {
31 addr = start_addr & (CFG_CACHELINE_SIZE - 1);
32 for (addr = start_addr;
33 addr < end_addr;
34 addr += CFG_CACHELINE_SIZE) {
35 asm ("dcbst 0,%0": :"r" (addr));
36 }
37 asm ("sync"); /* Wait for all dcbst to complete on bus */
38
39 for (addr = start_addr;
40 addr < end_addr;
41 addr += CFG_CACHELINE_SIZE) {
42 asm ("icbi 0,%0": :"r" (addr));
43 }
44 }
45 asm ("sync"); /* Always flush prefetch queue in any case */
46 asm ("isync");
47}