blob: 9a54a976d9323998320e63f919c3384306b0ecb2 [file] [log] [blame]
stroese771e05b2004-12-16 18:21:17 +00001/*
2 * (C) Copyright 2003
3 * Ingo Assmus <ingo.assmus@keymile.com>
4 *
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
stroese771e05b2004-12-16 18:21:17 +00009 */
10
11/********************************************************************************
12* gt64360r.h - GT-64360 Internal registers definition file.
13*
14* DESCRIPTION:
15* None.
16*
17* DEPENDENCIES:
18* None.
19*
20*******************************************************************************/
21
22#ifndef __INCmv_regsh
23#define __INCmv_regsh
24
25#define MV64360
26
27/* Supported by the Atlantis */
28#define MV64360_INCLUDE_PCI_1
29#define MV64360_INCLUDE_PCI_0_ARBITER
30#define MV64360_INCLUDE_PCI_1_ARBITER
31#define MV64360_INCLUDE_SNOOP_SUPPORT
32#define MV64360_INCLUDE_P2P
33#define MV64360_INCLUDE_ETH_PORT_2
34#define MV64360_INCLUDE_CPU_MAPPING
35#define MV64360_INCLUDE_MPSC
36
37/* Not supported features */
38#undef INCLUDE_CNTMR_4_7
39#undef INCLUDE_DMA_4_7
40
41/****************************************/
42/* Processor Address Space */
43/****************************************/
44
45/* DDR SDRAM BAR and size registers */
46
47#define MV64360_CS_0_BASE_ADDR 0x008
48#define MV64360_CS_0_SIZE 0x010
49#define MV64360_CS_1_BASE_ADDR 0x208
50#define MV64360_CS_1_SIZE 0x210
51#define MV64360_CS_2_BASE_ADDR 0x018
52#define MV64360_CS_2_SIZE 0x020
53#define MV64360_CS_3_BASE_ADDR 0x218
54#define MV64360_CS_3_SIZE 0x220
55
56/* Devices BAR and size registers */
57
58#define MV64360_DEV_CS0_BASE_ADDR 0x028
59#define MV64360_DEV_CS0_SIZE 0x030
60#define MV64360_DEV_CS1_BASE_ADDR 0x228
61#define MV64360_DEV_CS1_SIZE 0x230
62#define MV64360_DEV_CS2_BASE_ADDR 0x248
63#define MV64360_DEV_CS2_SIZE 0x250
64#define MV64360_DEV_CS3_BASE_ADDR 0x038
65#define MV64360_DEV_CS3_SIZE 0x040
66#define MV64360_BOOTCS_BASE_ADDR 0x238
67#define MV64360_BOOTCS_SIZE 0x240
68
69/* PCI 0 BAR and size registers */
70
71#define MV64360_PCI_0_IO_BASE_ADDR 0x048
72#define MV64360_PCI_0_IO_SIZE 0x050
73#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058
74#define MV64360_PCI_0_MEMORY0_SIZE 0x060
75#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080
76#define MV64360_PCI_0_MEMORY1_SIZE 0x088
77#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258
78#define MV64360_PCI_0_MEMORY2_SIZE 0x260
79#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280
80#define MV64360_PCI_0_MEMORY3_SIZE 0x288
81
82/* PCI 1 BAR and size registers */
83#define MV64360_PCI_1_IO_BASE_ADDR 0x090
84#define MV64360_PCI_1_IO_SIZE 0x098
85#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0
86#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8
87#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0
88#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8
89#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0
90#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8
91#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0
92#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8
93
94/* SRAM base address */
95#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268
96
97/* internal registers space base address */
98#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068
99
100/* Enables the CS , DEV_CS , PCI 0 and PCI 1
101 windows above */
102#define MV64360_BASE_ADDR_ENABLE 0x278
103
104/****************************************/
105/* PCI remap registers */
106/****************************************/
107 /* PCI 0 */
108#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0
109#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
110#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
111#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
112#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
113#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
114#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
115#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
116#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
117 /* PCI 1 */
118#define MV64360_PCI_1_IO_ADDR_REMAP 0x108
119#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
120#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
121#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
122#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
123#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
124#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
125#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
126#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
127
128#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
129#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
130#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
131#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
132#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
133#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
134#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
135#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
136
137/****************************************/
138/* CPU Control Registers */
139/****************************************/
140
141#define MV64360_CPU_CONFIG 0x000
142#define MV64360_CPU_MODE 0x120
143#define MV64360_CPU_MASTER_CONTROL 0x160
144#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150
145#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158
146#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168
147
148/****************************************/
149/* SMP RegisterS */
150/****************************************/
151
152#define MV64360_SMP_WHO_AM_I 0x200
153#define MV64360_SMP_CPU0_DOORBELL 0x214
154#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C
155#define MV64360_SMP_CPU1_DOORBELL 0x224
156#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C
157#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234
158#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C
159#define MV64360_SMP_SEMAPHOR0 0x244
160#define MV64360_SMP_SEMAPHOR1 0x24c
161#define MV64360_SMP_SEMAPHOR2 0x254
162#define MV64360_SMP_SEMAPHOR3 0x25c
163#define MV64360_SMP_SEMAPHOR4 0x264
164#define MV64360_SMP_SEMAPHOR5 0x26c
165#define MV64360_SMP_SEMAPHOR6 0x274
166#define MV64360_SMP_SEMAPHOR7 0x27c
167
168/****************************************/
169/* CPU Sync Barrier Register */
170/****************************************/
171
172#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
173#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
174#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
175#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
176
177/****************************************/
178/* CPU Access Protect */
179/****************************************/
180
181#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
182#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188
183#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
184#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198
185#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
186#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
187#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
188#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
189
190
191/****************************************/
192/* CPU Error Report */
193/****************************************/
194
195#define MV64360_CPU_ERROR_ADDR_LOW 0x070
196#define MV64360_CPU_ERROR_ADDR_HIGH 0x078
197#define MV64360_CPU_ERROR_DATA_LOW 0x128
198#define MV64360_CPU_ERROR_DATA_HIGH 0x130
199#define MV64360_CPU_ERROR_PARITY 0x138
200#define MV64360_CPU_ERROR_CAUSE 0x140
201#define MV64360_CPU_ERROR_MASK 0x148
202
203/****************************************/
204/* CPU Interface Debug Registers */
205/****************************************/
206
207#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360
208#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368
209#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370
210#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378
211#define MV64360_PUNIT_MMASK 0x3e4
212
213/****************************************/
214/* Integrated SRAM Registers */
215/****************************************/
216
217#define MV64360_SRAM_CONFIG 0x380
218#define MV64360_SRAM_TEST_MODE 0X3F4
219#define MV64360_SRAM_ERROR_CAUSE 0x388
220#define MV64360_SRAM_ERROR_ADDR 0x390
221#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8
222#define MV64360_SRAM_ERROR_DATA_LOW 0x398
223#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0
224#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8
225
226/****************************************/
227/* SDRAM Configuration */
228/****************************************/
229
230#define MV64360_SDRAM_CONFIG 0x1400
231#define MV64360_D_UNIT_CONTROL_LOW 0x1404
232#define MV64360_D_UNIT_CONTROL_HIGH 0x1424
233#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408
234#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c
235#define MV64360_SDRAM_ADDR_CONTROL 0x1410
236#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414
237#define MV64360_SDRAM_OPERATION 0x1418
238#define MV64360_SDRAM_MODE 0x141c
239#define MV64360_EXTENDED_DRAM_MODE 0x1420
240#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
241#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
242#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438
243#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
244#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4
245
246/****************************************/
247/* SDRAM Error Report */
248/****************************************/
249
250#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444
251#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440
252#define MV64360_SDRAM_ERROR_ADDR 0x1450
253#define MV64360_SDRAM_RECEIVED_ECC 0x1448
254#define MV64360_SDRAM_CALCULATED_ECC 0x144c
255#define MV64360_SDRAM_ECC_CONTROL 0x1454
256#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458
257
258/******************************************/
259/* Controlled Delay Line (CDL) Registers */
260/******************************************/
261
262#define MV64360_DFCDL_CONFIG0 0x1480
263#define MV64360_DFCDL_CONFIG1 0x1484
264#define MV64360_DLL_WRITE 0x1488
265#define MV64360_DLL_READ 0x148c
266#define MV64360_SRAM_ADDR 0x1490
267#define MV64360_SRAM_DATA0 0x1494
268#define MV64360_SRAM_DATA1 0x1498
269#define MV64360_SRAM_DATA2 0x149c
270#define MV64360_DFCL_PROBE 0x14a0
271
272/******************************************/
273/* Debug Registers */
274/******************************************/
275
276#define MV64360_DUNIT_DEBUG_LOW 0x1460
277#define MV64360_DUNIT_DEBUG_HIGH 0x1464
278#define MV64360_DUNIT_MMASK 0X1b40
279
280/****************************************/
281/* Device Parameters */
282/****************************************/
283
284#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c
285#define MV64360_DEVICE_BANK1_PARAMETERS 0x460
286#define MV64360_DEVICE_BANK2_PARAMETERS 0x464
287#define MV64360_DEVICE_BANK3_PARAMETERS 0x468
288#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c
289#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0
290#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
291#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
292#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
293
294/****************************************/
295/* Device interrupt registers */
296/****************************************/
297
298#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0
299#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4
300#define MV64360_DEVICE_ERROR_ADDR 0x4d8
301#define MV64360_DEVICE_ERROR_DATA 0x4dc
302#define MV64360_DEVICE_ERROR_PARITY 0x4e0
303
304/****************************************/
305/* Device debug registers */
306/****************************************/
307
308#define MV64360_DEVICE_DEBUG_LOW 0x4e4
309#define MV64360_DEVICE_DEBUG_HIGH 0x4e8
310#define MV64360_RUNIT_MMASK 0x4f0
311
312/****************************************/
313/* PCI Slave Address Decoding registers */
314/****************************************/
315
316#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08
317#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88
318#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08
319#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88
320#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c
321#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c
322#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c
323#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c
324#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10
325#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90
326#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10
327#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90
328#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18
329#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98
330#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14
331#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94
332#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
333#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
334#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
335#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
336#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
337#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
338#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24
339#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4
340#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28
341#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8
342#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
343#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
344#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
345#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
346#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
347#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
348#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
349#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
350#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
351#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
352#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
353#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
354#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
355#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
356#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
357#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
358#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
359#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
360#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
361#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
362#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
363#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
364#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
365#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
366#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
367#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
368#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
369#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
370#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
371#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
372#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
373#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
374#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
375#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
376#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
377#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
378#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
379#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
380#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
381#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
382#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
383#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
384#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
385#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
386#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
387#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
388#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
389#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
390#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
391#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
392#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c
393#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc
394#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
395#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
396#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44
397#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4
398#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48
399#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
400
401/***********************************/
402/* PCI Control Register Map */
403/***********************************/
404
405#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
406#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
407#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
408#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
409#define MV64360_PCI_0_COMMAND 0xc00
410#define MV64360_PCI_1_COMMAND 0xc80
411#define MV64360_PCI_0_MODE 0xd00
412#define MV64360_PCI_1_MODE 0xd80
413#define MV64360_PCI_0_RETRY 0xc04
414#define MV64360_PCI_1_RETRY 0xc84
415#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
416#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
417#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38
418#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8
419#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00
420#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80
421#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
422#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
423#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
424#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
425#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
426#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
427#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
428#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
429#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
430#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
431#define MV64360_PCI_0_P2P_CONFIG 0x1d14
432#define MV64360_PCI_1_P2P_CONFIG 0x1d94
433
434#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
435#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
436#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
437#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
438#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
439#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
440#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
441#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
442#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
443#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
444#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
445#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
446#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
447#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
448#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
449#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
450#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
451#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
452
453#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
454#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
455#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
456#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
457#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
458#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
459#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
460#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
461#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
462#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
463#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
464#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
465#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
466#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
467#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
468#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
469#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
470#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
471
472/****************************************/
473/* PCI Configuration Access Registers */
474/****************************************/
475
476#define MV64360_PCI_0_CONFIG_ADDR 0xcf8
477#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
478#define MV64360_PCI_1_CONFIG_ADDR 0xc78
479#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
480#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
481#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
482
483/****************************************/
484/* PCI Error Report Registers */
485/****************************************/
486
487#define MV64360_PCI_0_SERR_MASK 0xc28
488#define MV64360_PCI_1_SERR_MASK 0xca8
489#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40
490#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0
491#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44
492#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4
493#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48
494#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8
495#define MV64360_PCI_0_ERROR_COMMAND 0x1d50
496#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0
497#define MV64360_PCI_0_ERROR_CAUSE 0x1d58
498#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8
499#define MV64360_PCI_0_ERROR_MASK 0x1d5c
500#define MV64360_PCI_1_ERROR_MASK 0x1ddc
501
502/****************************************/
503/* PCI Debug Registers */
504/****************************************/
505
506#define MV64360_PCI_0_MMASK 0X1D24
507#define MV64360_PCI_1_MMASK 0X1DA4
508
509/*********************************************/
510/* PCI Configuration, Function 0, Registers */
511/*********************************************/
512
513#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000
514#define MV64360_PCI_STATUS_AND_COMMAND 0x004
515#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008
516#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
517
518#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010
519#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014
520#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018
521#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
522#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
523#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
524#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
525#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
526#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034
527#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C
528 /* capability list */
529#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
530#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
531#define MV64360_PCI_VPD_ADDR 0x048
532#define MV64360_PCI_VPD_DATA 0x04c
533#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050
534#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054
535#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
536#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c
537#define MV64360_PCI_X_COMMAND 0x060
538#define MV64360_PCI_X_STATUS 0x064
539#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068
540
541/***********************************************/
542/* PCI Configuration, Function 1, Registers */
543/***********************************************/
544
545#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110
546#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114
547#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118
548#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
549#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
550#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
551
552/***********************************************/
553/* PCI Configuration, Function 2, Registers */
554/***********************************************/
555
556#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
557#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
558#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
559#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
560#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
561#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
562
563/***********************************************/
564/* PCI Configuration, Function 3, Registers */
565/***********************************************/
566
567#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
568#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
569#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
570#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
571#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220
572#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224
573
574/***********************************************/
575/* PCI Configuration, Function 4, Registers */
576/***********************************************/
577
578#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
579#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
580#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
581#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
582#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420
583#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
584
585/****************************************/
586/* Messaging Unit Registers (I20) */
587/****************************************/
588
589#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
590#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
591#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
592#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
593#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
594#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
595#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
596#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
597#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
598#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
599#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
600#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
601#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
602#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
603#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
604#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
605#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
606#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
607#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
608#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
609#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
610#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
611
612#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
613#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
614#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
615#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
616#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
617#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
618#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
619#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
620#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
621#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
622#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
623#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
624#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
625#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
626#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
627#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
628#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
629#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
630#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
631#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
632#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
633#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
634
635#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
636#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
637#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
638#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
639#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
640#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
641#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
642#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
643#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
644#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
645#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
646#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
647#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
648#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
649#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
650#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
651#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
652#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
653#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
654#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
655#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
656#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
657#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
658#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
659#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
660#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
661#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
662#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
663#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
664#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
665#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
666#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
667#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
668#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
669#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
670#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
671#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
672#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
673#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
674#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
675#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
676#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
677#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
678#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
679
680/****************************************/
681/* Ethernet Unit Registers */
682/****************************************/
683
684#define MV64360_ETH_PHY_ADDR_REG 0x2000
685#define MV64360_ETH_SMI_REG 0x2004
686#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
687#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c
688#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
689#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
690#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc
691#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094
692#define MV64360_ETH_BAR_0 0x2200
693#define MV64360_ETH_BAR_1 0x2208
694#define MV64360_ETH_BAR_2 0x2210
695#define MV64360_ETH_BAR_3 0x2218
696#define MV64360_ETH_BAR_4 0x2220
697#define MV64360_ETH_BAR_5 0x2228
698#define MV64360_ETH_SIZE_REG_0 0x2204
699#define MV64360_ETH_SIZE_REG_1 0x220c
700#define MV64360_ETH_SIZE_REG_2 0x2214
701#define MV64360_ETH_SIZE_REG_3 0x221c
702#define MV64360_ETH_SIZE_REG_4 0x2224
703#define MV64360_ETH_SIZE_REG_5 0x222c
704#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230
705#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
706#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
707#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
708#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
709#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
710#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290
711#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
712#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
713#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
714#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
715#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
716#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
717#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
718#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
719#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
720#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
721#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10))
722#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10))
723#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10))
724#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10))
725#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10))
726#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10))
727#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10))
728#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
729#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
730#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
731#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
732#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
733#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
734#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
735#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
736#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
737#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
738#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
739#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
740#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
741#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
742#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
743#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
744#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
745#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
746#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
747#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
748#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
749#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
750#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
751#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
752#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
753#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
754#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
755#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
756#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
757#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
758#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
759#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
760#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
761#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
762#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
763#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
764#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
765#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
766#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
767#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
768#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
769#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
770#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
771#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
772#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
773#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
774#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
775#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
776#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
777#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
778#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
779#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
780#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
781#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
782#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
783#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
784#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
785#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
786#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
787#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
788#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
789#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
790#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
791#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
792#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
793#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
794
795/*******************************************/
796/* CUNIT Registers */
797/*******************************************/
798
799 /* Address Decoding Register Map */
800
801#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200
802#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208
803#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210
804#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218
805#define MV64360_CUNIT_SIZE0 0xf204
806#define MV64360_CUNIT_SIZE1 0xf20c
807#define MV64360_CUNIT_SIZE2 0xf214
808#define MV64360_CUNIT_SIZE3 0xf21c
809#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
810#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
811#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
812#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254
813#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258
814#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
815
816 /* Error Report Registers */
817
818#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310
819#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314
820#define MV64360_CUNIT_ERROR_ADDR 0xf318
821
822 /* Cunit Control Registers */
823
824#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300
825#define MV64360_CUNIT_CONFIG_REG 0xb40c
826#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
827
828 /* Cunit Debug Registers */
829
830#define MV64360_CUNIT_DEBUG_LOW 0xf340
831#define MV64360_CUNIT_DEBUG_HIGH 0xf344
832#define MV64360_CUNIT_MMASK 0xf380
833
834 /* Cunit Base Address Enable Window Bits*/
835#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0
836#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1
837#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2
838#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3
839
840 /* MPSCs Clocks Routing Registers */
841
842#define MV64360_MPSC_ROUTING_REG 0xb400
843#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404
844#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408
845
846 /* MPSCs Interrupts Registers */
847
848#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
849#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3))
850
851#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
852#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
853#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
854#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
855#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
856#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
857#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
858#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
859#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
860#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
861#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
862#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
863#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
864
865 /* MPSC0 Registers */
866
867
868/***************************************/
869/* SDMA Registers */
870/***************************************/
871
872#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
873#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
874#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
875#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
876#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
877
878#define MV64360_SDMA_CAUSE_REG 0xb800
879#define MV64360_SDMA_MASK_REG 0xb880
880
881
882/****************************************/
883/* SDMA Address Space Targets */
884/****************************************/
885
886#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00
887#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00
888#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00
889#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700
890
891#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01
892#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01
893#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01
894#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701
895
896#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00
897
898#define MV64360_SDMA_SRAM_TARGET 0x0003
899#define MV64360_SDMA_60X_BUS_TARGET 0x4003
900
901#define MV64360_PCI_0_TARGET 0x0003
902#define MV64360_PCI_1_TARGET 0x0004
903
904
905/* Devices BAR and size registers */
906
907#define MV64360_DEV_CS0_BASE_ADDR 0x028
908#define MV64360_DEV_CS0_SIZE 0x030
909#define MV64360_DEV_CS1_BASE_ADDR 0x228
910#define MV64360_DEV_CS1_SIZE 0x230
911#define MV64360_DEV_CS2_BASE_ADDR 0x248
912#define MV64360_DEV_CS2_SIZE 0x250
913#define MV64360_DEV_CS3_BASE_ADDR 0x038
914#define MV64360_DEV_CS3_SIZE 0x040
915#define MV64360_BOOTCS_BASE_ADDR 0x238
916#define MV64360_BOOTCS_SIZE 0x240
917
918/* SDMA Window access protection */
919#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
920#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
921#define MV64360_SDMA_WIN_ACCESS_FULL 2
922
923/* BRG Interrupts */
924
925#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
926#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3))
927#define MV64360_BRG_CAUSE_REG 0xb834
928#define MV64360_BRG_MASK_REG 0xb8b4
929
930/****************************************/
931/* DMA Channel Control */
932/****************************************/
933
934#define MV64360_DMA_CHANNEL0_CONTROL 0x840
935#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880
936#define MV64360_DMA_CHANNEL1_CONTROL 0x844
937#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884
938#define MV64360_DMA_CHANNEL2_CONTROL 0x848
939#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888
940#define MV64360_DMA_CHANNEL3_CONTROL 0x84C
941#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C
942
943
944/****************************************/
945/* IDMA Registers */
946/****************************************/
947
948#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800
949#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804
950#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808
951#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C
952#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810
953#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814
954#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818
955#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c
956#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820
957#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824
958#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828
959#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
960#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
961#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
962#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
963#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
964#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
965#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
966#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
967#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
968
969 /* IDMA Address Decoding Base Address Registers */
970
971#define MV64360_DMA_BASE_ADDR_REG0 0xa00
972#define MV64360_DMA_BASE_ADDR_REG1 0xa08
973#define MV64360_DMA_BASE_ADDR_REG2 0xa10
974#define MV64360_DMA_BASE_ADDR_REG3 0xa18
975#define MV64360_DMA_BASE_ADDR_REG4 0xa20
976#define MV64360_DMA_BASE_ADDR_REG5 0xa28
977#define MV64360_DMA_BASE_ADDR_REG6 0xa30
978#define MV64360_DMA_BASE_ADDR_REG7 0xa38
979
980 /* IDMA Address Decoding Size Address Register */
981
982#define MV64360_DMA_SIZE_REG0 0xa04
983#define MV64360_DMA_SIZE_REG1 0xa0c
984#define MV64360_DMA_SIZE_REG2 0xa14
985#define MV64360_DMA_SIZE_REG3 0xa1c
986#define MV64360_DMA_SIZE_REG4 0xa24
987#define MV64360_DMA_SIZE_REG5 0xa2c
988#define MV64360_DMA_SIZE_REG6 0xa34
989#define MV64360_DMA_SIZE_REG7 0xa3C
990
991 /* IDMA Address Decoding High Address Remap and Access
992 Protection Registers */
993
994#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60
995#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64
996#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68
997#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
998#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80
999#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
1000#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
1001#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
1002#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
1003#define MV64360_DMA_ARBITER_CONTROL 0x860
1004#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0
1005
1006 /* IDMA Headers Retarget Registers */
1007
1008#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84
1009#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88
1010
1011 /* IDMA Interrupt Register */
1012
1013#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0
1014#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4
1015#define MV64360_DMA_ERROR_ADDR 0x8c8
1016#define MV64360_DMA_ERROR_SELECT 0x8cc
1017
1018 /* IDMA Debug Register ( for internal use ) */
1019
1020#define MV64360_DMA_DEBUG_LOW 0x8e0
1021#define MV64360_DMA_DEBUG_HIGH 0x8e4
1022#define MV64360_DMA_SPARE 0xA8C
1023
1024/****************************************/
1025/* Timer_Counter */
1026/****************************************/
1027
1028#define MV64360_TIMER_COUNTER0 0x850
1029#define MV64360_TIMER_COUNTER1 0x854
1030#define MV64360_TIMER_COUNTER2 0x858
1031#define MV64360_TIMER_COUNTER3 0x85C
1032#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864
1033#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
1034#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
1035
1036/****************************************/
1037/* Watchdog registers */
1038/****************************************/
1039
1040#define MV64360_WATCHDOG_CONFIG_REG 0xb410
1041#define MV64360_WATCHDOG_VALUE_REG 0xb414
1042
1043/****************************************/
1044/* I2C Registers */
1045/****************************************/
1046
1047#define MV64360_I2C_SLAVE_ADDR 0xc000
1048#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010
1049#define MV64360_I2C_DATA 0xc004
1050#define MV64360_I2C_CONTROL 0xc008
1051#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C
1052#define MV64360_I2C_SOFT_RESET 0xc01c
1053
1054/****************************************/
1055/* GPP Interface Registers */
1056/****************************************/
1057
1058#define MV64360_GPP_IO_CONTROL 0xf100
1059#define MV64360_GPP_LEVEL_CONTROL 0xf110
1060#define MV64360_GPP_VALUE 0xf104
1061#define MV64360_GPP_INTERRUPT_CAUSE 0xf108
1062#define MV64360_GPP_INTERRUPT_MASK0 0xf10c
1063#define MV64360_GPP_INTERRUPT_MASK1 0xf114
1064#define MV64360_GPP_VALUE_SET 0xf118
1065#define MV64360_GPP_VALUE_CLEAR 0xf11c
1066
1067/****************************************/
1068/* Interrupt Controller Registers */
1069/****************************************/
1070
1071/****************************************/
1072/* Interrupts */
1073/****************************************/
1074
1075#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004
1076#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
1077#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014
1078#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c
1079#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024
1080#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034
1081#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c
1082#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044
1083#define MV64360_INTERRUPT0_MASK_0_LOW 0x054
1084#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c
1085#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064
1086#define MV64360_INTERRUPT1_MASK_0_LOW 0x074
1087#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c
1088#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084
1089
1090/****************************************/
1091/* MPP Interface Registers */
1092/****************************************/
1093
1094#define MV64360_MPP_CONTROL0 0xf000
1095#define MV64360_MPP_CONTROL1 0xf004
1096#define MV64360_MPP_CONTROL2 0xf008
1097#define MV64360_MPP_CONTROL3 0xf00c
1098
1099/****************************************/
1100/* Serial Initialization registers */
1101/****************************************/
1102
1103#define MV64360_SERIAL_INIT_LAST_DATA 0xf324
1104#define MV64360_SERIAL_INIT_CONTROL 0xf328
1105#define MV64360_SERIAL_INIT_STATUS 0xf32c
1106
1107
1108#endif /* __INCgt64360rh */