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Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
Xie Xiaoboae2044d2011-10-03 12:18:39 -07002 * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/mmu.h>
Kumar Gala7c0d4a72008-09-22 14:11:11 -050028#include <asm/cache.h>
Kumar Gala9490a7f2008-07-25 13:31:05 -050029#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050030#include <asm/fsl_pci.h>
Kumar Gala9490a7f2008-07-25 13:31:05 -050031#include <asm/fsl_ddr_sdram.h>
32#include <asm/io.h>
Kumar Gala54648982010-04-20 10:21:12 -050033#include <asm/fsl_serdes.h>
Kumar Gala9490a7f2008-07-25 13:31:05 -050034#include <spd.h>
35#include <miiphy.h>
36#include <libfdt.h>
37#include <spd_sdram.h>
38#include <fdt_support.h>
Andy Fleming063c1262011-04-08 02:10:54 -050039#include <fsl_mdio.h>
Jason Jin2e26d832008-10-10 11:41:00 +080040#include <tsec.h>
41#include <netdev.h>
Wolfgang Denk54a7cc42009-01-28 09:25:31 +010042#include <sata.h>
Kumar Gala9490a7f2008-07-25 13:31:05 -050043
Jason Jin2e26d832008-10-10 11:41:00 +080044#include "../common/sgmii_riser.h"
Kumar Gala9490a7f2008-07-25 13:31:05 -050045
Andy Fleming80522dc2008-10-30 16:51:33 -050046int board_early_init_f (void)
47{
48#ifdef CONFIG_MMC
49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50
51 setbits_be32(&gur->pmuxcr,
Xie Xiaoboae2044d2011-10-03 12:18:39 -070052 (MPC85xx_PMUXCR_SDHC_CD |
Andy Fleming80522dc2008-10-30 16:51:33 -050053 MPC85xx_PMUXCR_SDHC_WP));
Xie Xiaobo8af3d222011-10-03 12:18:40 -070054
55 /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
56 * however, this erratum only applies to MPC8536 Rev1.0.
57 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
58 if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
59 (SVR_MIN(get_svr()) >= 0x1))
60 || (SVR_MAJ(get_svr() & 0x7) > 0x1))
61 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
Andy Fleming80522dc2008-10-30 16:51:33 -050062#endif
63 return 0;
64}
65
Kumar Gala9490a7f2008-07-25 13:31:05 -050066int checkboard (void)
67{
Kumar Gala6bb5b412009-07-14 22:42:01 -050068 u8 vboot;
69 u8 *pixis_base = (u8 *)PIXIS_BASE;
70
Timur Tabi5d065c32012-03-15 11:42:27 +000071 printf("Board: MPC8536DS Sys ID: 0x%02x, "
Kumar Gala6bb5b412009-07-14 22:42:01 -050072 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
74 in_8(pixis_base + PIXIS_PVER));
75
76 vboot = in_8(pixis_base + PIXIS_VBOOT);
77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
78 case PIXIS_VBOOT_LBMAP_NOR0:
79 puts ("vBank: 0\n");
80 break;
81 case PIXIS_VBOOT_LBMAP_NOR1:
82 puts ("vBank: 1\n");
83 break;
84 case PIXIS_VBOOT_LBMAP_NOR2:
85 puts ("vBank: 2\n");
86 break;
87 case PIXIS_VBOOT_LBMAP_NOR3:
88 puts ("vBank: 3\n");
89 break;
90 case PIXIS_VBOOT_LBMAP_PJET:
91 puts ("Promjet\n");
92 break;
93 case PIXIS_VBOOT_LBMAP_NAND:
94 puts ("NAND\n");
95 break;
96 }
97
Kumar Gala9490a7f2008-07-25 13:31:05 -050098 return 0;
99}
100
Kumar Gala9490a7f2008-07-25 13:31:05 -0500101#if !defined(CONFIG_SPD_EEPROM)
102/*
103 * Fixed sdram init -- doesn't use serial presence detect.
104 */
105
106phys_size_t fixed_sdram (void)
107{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Kumar Gala9490a7f2008-07-25 13:31:05 -0500109 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
110 uint d_init;
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
113 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
Kumar Gala9490a7f2008-07-25 13:31:05 -0500114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
116 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
117 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
118 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
119 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
120 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
121 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
122 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
123 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
124 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Kumar Gala9490a7f2008-07-25 13:31:05 -0500125
126#if defined (CONFIG_DDR_ECC)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
128 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
129 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
Kumar Gala9490a7f2008-07-25 13:31:05 -0500130#endif
131 asm("sync;isync");
132
133 udelay(500);
134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Kumar Gala9490a7f2008-07-25 13:31:05 -0500136
137#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
138 d_init = 1;
139 debug("DDR - 1st controller: memory initializing\n");
140 /*
141 * Poll until memory is initialized.
142 * 512 Meg at 400 might hit this 200 times or so.
143 */
144 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
145 udelay(1000);
146 }
147 debug("DDR: memory initialized\n\n");
148 asm("sync; isync");
149 udelay(500);
150#endif
151
152 return 512 * 1024 * 1024;
153}
154
155#endif
156
157#ifdef CONFIG_PCI1
158static struct pci_controller pci1_hose;
159#endif
160
Mingkai Hu8a414c42009-10-28 10:49:31 +0800161#ifdef CONFIG_PCI
162void pci_init_board(void)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500163{
Mingkai Hu8a414c42009-10-28 10:49:31 +0800164 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600165 struct fsl_pci_info pci_info;
166 u32 devdisr, pordevsr;
Mingkai Hu8a414c42009-10-28 10:49:31 +0800167 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600168 int first_free_busno;
Kumar Gala9490a7f2008-07-25 13:31:05 -0500169
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600170 first_free_busno = fsl_pcie_init_board(0);
Mingkai Hu8a414c42009-10-28 10:49:31 +0800171
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600172#ifdef CONFIG_PCI1
Mingkai Hu8a414c42009-10-28 10:49:31 +0800173 devdisr = in_be32(&gur->devdisr);
174 pordevsr = in_be32(&gur->pordevsr);
175 porpllsr = in_be32(&gur->porpllsr);
Mingkai Hu8a414c42009-10-28 10:49:31 +0800176
Mingkai Hu8a414c42009-10-28 10:49:31 +0800177 pci_speed = 66666000;
178 pci_32 = 1;
179 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
180 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
Kumar Gala9490a7f2008-07-25 13:31:05 -0500181
Kumar Gala9490a7f2008-07-25 13:31:05 -0500182 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600183 SET_STD_PCI_INFO(pci_info, 1);
184 set_next_law(pci_info.mem_phys,
185 law_size_bits(pci_info.mem_size), pci_info.law);
186 set_next_law(pci_info.io_phys,
187 law_size_bits(pci_info.io_size), pci_info.law);
188
189 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500190 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
Kumar Gala9490a7f2008-07-25 13:31:05 -0500191 (pci_32) ? 32 : 64,
192 (pci_speed == 33333000) ? "33" :
193 (pci_speed == 66666000) ? "66" : "unknown",
194 pci_clk_sel ? "sync" : "async",
195 pci_agent ? "agent" : "host",
196 pci_arb ? "arbiter" : "external-arbiter",
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600197 pci_info.regs);
Kumar Gala9490a7f2008-07-25 13:31:05 -0500198
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600199 first_free_busno = fsl_pci_init_port(&pci_info,
Mingkai Hu8a414c42009-10-28 10:49:31 +0800200 &pci1_hose, first_free_busno);
Kumar Gala9490a7f2008-07-25 13:31:05 -0500201 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500202 printf("PCI: disabled\n");
Kumar Gala9490a7f2008-07-25 13:31:05 -0500203 }
Mingkai Hu8a414c42009-10-28 10:49:31 +0800204
205 puts("\n");
Kumar Gala9490a7f2008-07-25 13:31:05 -0500206#else
Mingkai Hu8a414c42009-10-28 10:49:31 +0800207 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500208#endif
209}
Mingkai Hu8a414c42009-10-28 10:49:31 +0800210#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500211
Kumar Gala9490a7f2008-07-25 13:31:05 -0500212int board_early_init_r(void)
213{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
Kumar Gala5fb6ea32009-11-13 09:25:07 -0600215 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
Kumar Gala9490a7f2008-07-25 13:31:05 -0500216
217 /*
218 * Remap Boot flash + PROMJET region to caching-inhibited
219 * so that flash can be erased properly.
220 */
221
Kumar Gala7c0d4a72008-09-22 14:11:11 -0500222 /* Flush d-cache and invalidate i-cache of any FLASH data */
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100223 flush_dcache();
224 invalidate_icache();
Kumar Gala9490a7f2008-07-25 13:31:05 -0500225
226 /* invalidate existing TLB entry for flash + promjet */
227 disable_tlb(flash_esel);
228
Kumar Galac953ddf2008-12-02 14:19:34 -0600229 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500230 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
231 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
232
233 return 0;
234}
235
Jason Jin2e26d832008-10-10 11:41:00 +0800236int board_eth_init(bd_t *bis)
237{
238#ifdef CONFIG_TSEC_ENET
Andy Fleming063c1262011-04-08 02:10:54 -0500239 struct fsl_pq_mdio_info mdio_info;
Jason Jin2e26d832008-10-10 11:41:00 +0800240 struct tsec_info_struct tsec_info[2];
Jason Jin2e26d832008-10-10 11:41:00 +0800241 int num = 0;
Jason Jin2e26d832008-10-10 11:41:00 +0800242
243#ifdef CONFIG_TSEC1
244 SET_STD_TSEC_INFO(tsec_info[num], 1);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600245 if (is_serdes_configured(SGMII_TSEC1)) {
246 puts("eTSEC1 is in sgmii mode.\n");
Jason Jin2e26d832008-10-10 11:41:00 +0800247 tsec_info[num].phyaddr = 0;
248 tsec_info[num].flags |= TSEC_SGMII;
249 }
250 num++;
251#endif
252#ifdef CONFIG_TSEC3
253 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600254 if (is_serdes_configured(SGMII_TSEC3)) {
255 puts("eTSEC3 is in sgmii mode.\n");
Jason Jin2e26d832008-10-10 11:41:00 +0800256 tsec_info[num].phyaddr = 1;
257 tsec_info[num].flags |= TSEC_SGMII;
258 }
259 num++;
260#endif
261
262 if (!num) {
263 printf("No TSECs initialized\n");
264 return 0;
265 }
266
Andy Flemingfeede8b2008-12-05 20:10:22 -0600267#ifdef CONFIG_FSL_SGMII_RISER
Kumar Gala058d7dc2010-12-16 14:28:06 -0600268 if (is_serdes_configured(SGMII_TSEC1) ||
269 is_serdes_configured(SGMII_TSEC3)) {
Jason Jin2e26d832008-10-10 11:41:00 +0800270 fsl_sgmii_riser_init(tsec_info, num);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600271 }
Andy Flemingfeede8b2008-12-05 20:10:22 -0600272#endif
Jason Jin2e26d832008-10-10 11:41:00 +0800273
Andy Fleming063c1262011-04-08 02:10:54 -0500274 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
275 mdio_info.name = DEFAULT_MII_NAME;
276 fsl_pq_mdio_init(bis, &mdio_info);
277
Jason Jin2e26d832008-10-10 11:41:00 +0800278 tsec_eth_init(bis, tsec_info, num);
279#endif
280 return pci_eth_init(bis);
281}
282
Kumar Gala9490a7f2008-07-25 13:31:05 -0500283#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500284void ft_board_setup(void *blob, bd_t *bd)
285{
Kumar Gala9490a7f2008-07-25 13:31:05 -0500286 ft_cpu_setup(blob, bd);
287
Kumar Gala6525d512010-07-08 22:37:44 -0500288 FT_FSL_PCI_SETUP;
289
Andy Flemingfeede8b2008-12-05 20:10:22 -0600290#ifdef CONFIG_FSL_SGMII_RISER
291 fsl_sgmii_riser_fdt_fixup(blob);
292#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500293}
294#endif