blob: 456c1b4cc92321616141fa0feaebe5ebedb06e67 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming272cc702008-10-30 16:41:01 -05002/*
3 * Copyright 2008, Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based vaguely on the Linux code
Andy Fleming272cc702008-10-30 16:41:01 -05007 */
8
9#include <config.h>
10#include <common.h>
11#include <command.h>
Sjoerd Simons8e3332e2015-08-30 16:55:45 -060012#include <dm.h>
13#include <dm/device-internal.h>
Stephen Warrend4622df2014-05-23 12:47:06 -060014#include <errno.h>
Andy Fleming272cc702008-10-30 16:41:01 -050015#include <mmc.h>
16#include <part.h>
Peng Fan2051aef2016-10-11 15:08:43 +080017#include <power/regulator.h>
Andy Fleming272cc702008-10-30 16:41:01 -050018#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060019#include <memalign.h>
Andy Fleming272cc702008-10-30 16:41:01 -050020#include <linux/list.h>
Rabin Vincent9b1f9422009-04-05 13:30:54 +053021#include <div64.h>
Paul Burtonda61fa52013-09-09 15:30:26 +010022#include "mmc_private.h"
Andy Fleming272cc702008-10-30 16:41:01 -050023
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +020024static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +020025static int mmc_power_cycle(struct mmc *mmc);
Marek Vasut62d77ce2018-04-15 00:37:11 +020026#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +020027static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
Marek Vasutb5b838f2016-12-01 02:06:33 +010028#endif
29
Simon Glasse7881d82017-07-29 11:35:31 -060030#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020031
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010032#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020033static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
34{
35 return -ENOSYS;
36}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010037#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020038
Jeroen Hofstee750121c2014-07-12 21:24:08 +020039__weak int board_mmc_getwp(struct mmc *mmc)
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +000040{
41 return -1;
42}
43
44int mmc_getwp(struct mmc *mmc)
45{
46 int wp;
47
48 wp = board_mmc_getwp(mmc);
49
Peter Korsgaardd4e1da42013-03-21 04:00:03 +000050 if (wp < 0) {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020051 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
Peter Korsgaardd4e1da42013-03-21 04:00:03 +000053 else
54 wp = 0;
55 }
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +000056
57 return wp;
58}
59
Jeroen Hofsteecee9ab72014-07-10 22:46:28 +020060__weak int board_mmc_getcd(struct mmc *mmc)
61{
Stefano Babic11fdade2010-02-05 15:04:43 +010062 return -1;
63}
Simon Glass8ca51e52016-06-12 23:30:22 -060064#endif
Stefano Babic11fdade2010-02-05 15:04:43 +010065
Marek Vasut8635ff92012-03-15 18:41:35 +000066#ifdef CONFIG_MMC_TRACE
Simon Glassc0c76eb2016-06-12 23:30:20 -060067void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
68{
69 printf("CMD_SEND:%d\n", cmd->cmdidx);
Marek Vasut7d5ccb12019-03-23 18:54:45 +010070 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
Simon Glassc0c76eb2016-06-12 23:30:20 -060071}
72
73void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
74{
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +000075 int i;
76 u8 *ptr;
77
Bin Meng7863ce52016-03-17 21:53:14 -070078 if (ret) {
79 printf("\t\tRET\t\t\t %d\n", ret);
80 } else {
81 switch (cmd->resp_type) {
82 case MMC_RSP_NONE:
83 printf("\t\tMMC_RSP_NONE\n");
84 break;
85 case MMC_RSP_R1:
Marek Vasut7d5ccb12019-03-23 18:54:45 +010086 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
Bin Meng7863ce52016-03-17 21:53:14 -070087 cmd->response[0]);
88 break;
89 case MMC_RSP_R1b:
Marek Vasut7d5ccb12019-03-23 18:54:45 +010090 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
Bin Meng7863ce52016-03-17 21:53:14 -070091 cmd->response[0]);
92 break;
93 case MMC_RSP_R2:
Marek Vasut7d5ccb12019-03-23 18:54:45 +010094 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
Bin Meng7863ce52016-03-17 21:53:14 -070095 cmd->response[0]);
Marek Vasut7d5ccb12019-03-23 18:54:45 +010096 printf("\t\t \t\t 0x%08x \n",
Bin Meng7863ce52016-03-17 21:53:14 -070097 cmd->response[1]);
Marek Vasut7d5ccb12019-03-23 18:54:45 +010098 printf("\t\t \t\t 0x%08x \n",
Bin Meng7863ce52016-03-17 21:53:14 -070099 cmd->response[2]);
Marek Vasut7d5ccb12019-03-23 18:54:45 +0100100 printf("\t\t \t\t 0x%08x \n",
Bin Meng7863ce52016-03-17 21:53:14 -0700101 cmd->response[3]);
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +0000102 printf("\n");
Bin Meng7863ce52016-03-17 21:53:14 -0700103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
105 int j;
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
108 ptr += 3;
109 for (j = 0; j < 4; j++)
Marek Vasut7d5ccb12019-03-23 18:54:45 +0100110 printf("%02x ", *ptr--);
Bin Meng7863ce52016-03-17 21:53:14 -0700111 printf("\n");
112 }
113 break;
114 case MMC_RSP_R3:
Marek Vasut7d5ccb12019-03-23 18:54:45 +0100115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
Bin Meng7863ce52016-03-17 21:53:14 -0700116 cmd->response[0]);
117 break;
118 default:
119 printf("\t\tERROR MMC rsp not supported\n");
120 break;
Bin Meng53e8e402016-03-17 21:53:13 -0700121 }
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +0000122 }
Simon Glassc0c76eb2016-06-12 23:30:20 -0600123}
124
125void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
126{
127 int status;
128
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
131}
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +0000132#endif
Simon Glassc0c76eb2016-06-12 23:30:20 -0600133
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200134#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135const char *mmc_mode_name(enum bus_mode mode)
136{
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
139 [SD_LEGACY] = "SD Legacy",
140 [MMC_HS] = "MMC High Speed (26MHz)",
141 [SD_HS] = "SD High Speed (50MHz)",
142 [UHS_SDR12] = "UHS SDR12 (25MHz)",
143 [UHS_SDR25] = "UHS SDR25 (50MHz)",
144 [UHS_SDR50] = "UHS SDR50 (100MHz)",
145 [UHS_SDR104] = "UHS SDR104 (208MHz)",
146 [UHS_DDR50] = "UHS DDR50 (50MHz)",
147 [MMC_HS_52] = "MMC High Speed (52MHz)",
148 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
149 [MMC_HS_200] = "HS200 (200MHz)",
Peng Fan3dd26262018-08-10 14:07:54 +0800150 [MMC_HS_400] = "HS400 (200MHz)",
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200151 };
152
153 if (mode >= MMC_MODES_END)
154 return "Unknown mode";
155 else
156 return names[mode];
157}
158#endif
159
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200160static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
161{
162 static const int freqs[] = {
Jaehoon Chung1b313aa2018-01-30 14:10:16 +0900163 [MMC_LEGACY] = 25000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200164 [SD_LEGACY] = 25000000,
165 [MMC_HS] = 26000000,
166 [SD_HS] = 50000000,
Jaehoon Chung1b313aa2018-01-30 14:10:16 +0900167 [MMC_HS_52] = 52000000,
168 [MMC_DDR_52] = 52000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200169 [UHS_SDR12] = 25000000,
170 [UHS_SDR25] = 50000000,
171 [UHS_SDR50] = 100000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200172 [UHS_DDR50] = 50000000,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100173 [UHS_SDR104] = 208000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200174 [MMC_HS_200] = 200000000,
Peng Fan3dd26262018-08-10 14:07:54 +0800175 [MMC_HS_400] = 200000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200176 };
177
178 if (mode == MMC_LEGACY)
179 return mmc->legacy_speed;
180 else if (mode >= MMC_MODES_END)
181 return 0;
182 else
183 return freqs[mode];
184}
185
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200186static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
187{
188 mmc->selected_mode = mode;
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200189 mmc->tran_speed = mmc_mode2freq(mmc, mode);
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200190 mmc->ddr_mode = mmc_is_mode_ddr(mode);
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900191 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
192 mmc->tran_speed / 1000000);
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200193 return 0;
194}
195
Simon Glasse7881d82017-07-29 11:35:31 -0600196#if !CONFIG_IS_ENABLED(DM_MMC)
Simon Glassc0c76eb2016-06-12 23:30:20 -0600197int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
198{
199 int ret;
200
201 mmmc_trace_before_send(mmc, cmd);
202 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
203 mmmc_trace_after_send(mmc, cmd, ret);
204
Marek Vasut8635ff92012-03-15 18:41:35 +0000205 return ret;
Andy Fleming272cc702008-10-30 16:41:01 -0500206}
Simon Glass8ca51e52016-06-12 23:30:22 -0600207#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500208
Paul Burtonda61fa52013-09-09 15:30:26 +0100209int mmc_send_status(struct mmc *mmc, int timeout)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000210{
211 struct mmc_cmd cmd;
Jan Kloetzked617c422012-02-05 22:29:12 +0000212 int err, retries = 5;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000213
214 cmd.cmdidx = MMC_CMD_SEND_STATUS;
215 cmd.resp_type = MMC_RSP_R1;
Marek Vasutaaf3d412011-08-10 09:24:48 +0200216 if (!mmc_host_is_spi(mmc))
217 cmd.cmdarg = mmc->rca << 16;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000218
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500219 while (1) {
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000220 err = mmc_send_cmd(mmc, &cmd, NULL);
Jan Kloetzked617c422012-02-05 22:29:12 +0000221 if (!err) {
222 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
223 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
224 MMC_STATE_PRG)
225 break;
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +0200226
227 if (cmd.response[0] & MMC_STATUS_MASK) {
Paul Burton56196822013-09-04 16:12:25 +0100228#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Marek Vasut7d5ccb12019-03-23 18:54:45 +0100229 pr_err("Status Error: 0x%08x\n",
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100230 cmd.response[0]);
Paul Burton56196822013-09-04 16:12:25 +0100231#endif
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900232 return -ECOMM;
Jan Kloetzked617c422012-02-05 22:29:12 +0000233 }
234 } else if (--retries < 0)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000235 return err;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000236
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500237 if (timeout-- <= 0)
238 break;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000239
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500240 udelay(1000);
241 }
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000242
Simon Glassc0c76eb2016-06-12 23:30:20 -0600243 mmc_trace_state(mmc, &cmd);
Jongman Heo5b0c9422012-06-03 21:32:13 +0000244 if (timeout <= 0) {
Paul Burton56196822013-09-04 16:12:25 +0100245#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100246 pr_err("Timeout waiting card ready\n");
Paul Burton56196822013-09-04 16:12:25 +0100247#endif
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900248 return -ETIMEDOUT;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000249 }
250
251 return 0;
252}
253
Paul Burtonda61fa52013-09-09 15:30:26 +0100254int mmc_set_blocklen(struct mmc *mmc, int len)
Andy Fleming272cc702008-10-30 16:41:01 -0500255{
256 struct mmc_cmd cmd;
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200257 int err;
Andy Fleming272cc702008-10-30 16:41:01 -0500258
Andrew Gabbasov786e8f82014-12-01 06:59:09 -0600259 if (mmc->ddr_mode)
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900260 return 0;
261
Andy Fleming272cc702008-10-30 16:41:01 -0500262 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
263 cmd.resp_type = MMC_RSP_R1;
264 cmd.cmdarg = len;
Andy Fleming272cc702008-10-30 16:41:01 -0500265
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200266 err = mmc_send_cmd(mmc, &cmd, NULL);
267
268#ifdef CONFIG_MMC_QUIRKS
269 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
270 int retries = 4;
271 /*
272 * It has been seen that SET_BLOCKLEN may fail on the first
273 * attempt, let's try a few more time
274 */
275 do {
276 err = mmc_send_cmd(mmc, &cmd, NULL);
277 if (!err)
278 break;
279 } while (retries--);
280 }
281#endif
282
283 return err;
Andy Fleming272cc702008-10-30 16:41:01 -0500284}
285
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100286#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200287static const u8 tuning_blk_pattern_4bit[] = {
288 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
289 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
290 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
291 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
292 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
293 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
294 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
295 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
296};
297
298static const u8 tuning_blk_pattern_8bit[] = {
299 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
300 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
301 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
302 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
303 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
304 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
305 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
306 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
307 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
308 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
309 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
310 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
311 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
312 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
313 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
314 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
315};
316
317int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
318{
319 struct mmc_cmd cmd;
320 struct mmc_data data;
321 const u8 *tuning_block_pattern;
322 int size, err;
323
324 if (mmc->bus_width == 8) {
325 tuning_block_pattern = tuning_blk_pattern_8bit;
326 size = sizeof(tuning_blk_pattern_8bit);
327 } else if (mmc->bus_width == 4) {
328 tuning_block_pattern = tuning_blk_pattern_4bit;
329 size = sizeof(tuning_blk_pattern_4bit);
330 } else {
331 return -EINVAL;
332 }
333
334 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
335
336 cmd.cmdidx = opcode;
337 cmd.cmdarg = 0;
338 cmd.resp_type = MMC_RSP_R1;
339
340 data.dest = (void *)data_buf;
341 data.blocks = 1;
342 data.blocksize = size;
343 data.flags = MMC_DATA_READ;
344
345 err = mmc_send_cmd(mmc, &cmd, &data);
346 if (err)
347 return err;
348
349 if (memcmp(data_buf, tuning_block_pattern, size))
350 return -EIO;
351
352 return 0;
353}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100354#endif
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200355
Sascha Silbeff8fef52013-06-14 13:07:25 +0200356static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
Kim Phillipsfdbb8732012-10-29 13:34:43 +0000357 lbaint_t blkcnt)
Andy Fleming272cc702008-10-30 16:41:01 -0500358{
359 struct mmc_cmd cmd;
360 struct mmc_data data;
361
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700362 if (blkcnt > 1)
363 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
364 else
365 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
Andy Fleming272cc702008-10-30 16:41:01 -0500366
367 if (mmc->high_capacity)
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700368 cmd.cmdarg = start;
Andy Fleming272cc702008-10-30 16:41:01 -0500369 else
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700370 cmd.cmdarg = start * mmc->read_bl_len;
Andy Fleming272cc702008-10-30 16:41:01 -0500371
372 cmd.resp_type = MMC_RSP_R1;
Andy Fleming272cc702008-10-30 16:41:01 -0500373
374 data.dest = dst;
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700375 data.blocks = blkcnt;
Andy Fleming272cc702008-10-30 16:41:01 -0500376 data.blocksize = mmc->read_bl_len;
377 data.flags = MMC_DATA_READ;
378
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700379 if (mmc_send_cmd(mmc, &cmd, &data))
380 return 0;
Andy Fleming272cc702008-10-30 16:41:01 -0500381
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700382 if (blkcnt > 1) {
383 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
384 cmd.cmdarg = 0;
385 cmd.resp_type = MMC_RSP_R1b;
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700386 if (mmc_send_cmd(mmc, &cmd, NULL)) {
Paul Burton56196822013-09-04 16:12:25 +0100387#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100388 pr_err("mmc fail to send stop cmd\n");
Paul Burton56196822013-09-04 16:12:25 +0100389#endif
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700390 return 0;
391 }
Andy Fleming272cc702008-10-30 16:41:01 -0500392 }
393
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700394 return blkcnt;
Andy Fleming272cc702008-10-30 16:41:01 -0500395}
396
Simon Glassc4d660d2017-07-04 13:31:19 -0600397#if CONFIG_IS_ENABLED(BLK)
Simon Glass7dba0b92016-06-12 23:30:15 -0600398ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
Simon Glass33fb2112016-05-01 13:52:41 -0600399#else
Simon Glass7dba0b92016-06-12 23:30:15 -0600400ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
401 void *dst)
Simon Glass33fb2112016-05-01 13:52:41 -0600402#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500403{
Simon Glassc4d660d2017-07-04 13:31:19 -0600404#if CONFIG_IS_ENABLED(BLK)
Simon Glass33fb2112016-05-01 13:52:41 -0600405 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
406#endif
Simon Glassbcce53d2016-02-29 15:25:51 -0700407 int dev_num = block_dev->devnum;
Stephen Warren873cc1d2015-12-07 11:38:49 -0700408 int err;
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700409 lbaint_t cur, blocks_todo = blkcnt;
Andy Fleming272cc702008-10-30 16:41:01 -0500410
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700411 if (blkcnt == 0)
412 return 0;
413
414 struct mmc *mmc = find_mmc_device(dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500415 if (!mmc)
416 return 0;
417
Marek Vasutb5b838f2016-12-01 02:06:33 +0100418 if (CONFIG_IS_ENABLED(MMC_TINY))
419 err = mmc_switch_part(mmc, block_dev->hwpart);
420 else
421 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
422
Stephen Warren873cc1d2015-12-07 11:38:49 -0700423 if (err < 0)
424 return 0;
425
Simon Glassc40fdca2016-05-01 13:52:35 -0600426 if ((start + blkcnt) > block_dev->lba) {
Paul Burton56196822013-09-04 16:12:25 +0100427#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100428 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
429 start + blkcnt, block_dev->lba);
Paul Burton56196822013-09-04 16:12:25 +0100430#endif
Lei Wend2bf29e2010-09-13 22:07:27 +0800431 return 0;
432 }
Andy Fleming272cc702008-10-30 16:41:01 -0500433
Simon Glass11692992015-06-23 15:38:50 -0600434 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900435 pr_debug("%s: Failed to set blocklen\n", __func__);
Andy Fleming272cc702008-10-30 16:41:01 -0500436 return 0;
Simon Glass11692992015-06-23 15:38:50 -0600437 }
Andy Fleming272cc702008-10-30 16:41:01 -0500438
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700439 do {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200440 cur = (blocks_todo > mmc->cfg->b_max) ?
441 mmc->cfg->b_max : blocks_todo;
Simon Glass11692992015-06-23 15:38:50 -0600442 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900443 pr_debug("%s: Failed to read blocks\n", __func__);
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700444 return 0;
Simon Glass11692992015-06-23 15:38:50 -0600445 }
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700446 blocks_todo -= cur;
447 start += cur;
448 dst += cur * mmc->read_bl_len;
449 } while (blocks_todo > 0);
Andy Fleming272cc702008-10-30 16:41:01 -0500450
451 return blkcnt;
452}
453
Kim Phillipsfdbb8732012-10-29 13:34:43 +0000454static int mmc_go_idle(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -0500455{
456 struct mmc_cmd cmd;
457 int err;
458
459 udelay(1000);
460
461 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
462 cmd.cmdarg = 0;
463 cmd.resp_type = MMC_RSP_NONE;
Andy Fleming272cc702008-10-30 16:41:01 -0500464
465 err = mmc_send_cmd(mmc, &cmd, NULL);
466
467 if (err)
468 return err;
469
470 udelay(2000);
471
472 return 0;
473}
474
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100475#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200476static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
477{
478 struct mmc_cmd cmd;
479 int err = 0;
480
481 /*
482 * Send CMD11 only if the request is to switch the card to
483 * 1.8V signalling.
484 */
485 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
486 return mmc_set_signal_voltage(mmc, signal_voltage);
487
488 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
489 cmd.cmdarg = 0;
490 cmd.resp_type = MMC_RSP_R1;
491
492 err = mmc_send_cmd(mmc, &cmd, NULL);
493 if (err)
494 return err;
495
496 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
497 return -EIO;
498
499 /*
500 * The card should drive cmd and dat[0:3] low immediately
501 * after the response of cmd11, but wait 100 us to be sure
502 */
503 err = mmc_wait_dat0(mmc, 0, 100);
504 if (err == -ENOSYS)
505 udelay(100);
506 else if (err)
507 return -ETIMEDOUT;
508
509 /*
510 * During a signal voltage level switch, the clock must be gated
511 * for 5 ms according to the SD spec
512 */
Jaehoon Chung65117182018-01-26 19:25:29 +0900513 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200514
515 err = mmc_set_signal_voltage(mmc, signal_voltage);
516 if (err)
517 return err;
518
519 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
520 mdelay(10);
Jaehoon Chung65117182018-01-26 19:25:29 +0900521 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200522
523 /*
524 * Failure to switch is indicated by the card holding
525 * dat[0:3] low. Wait for at least 1 ms according to spec
526 */
527 err = mmc_wait_dat0(mmc, 1, 1000);
528 if (err == -ENOSYS)
529 udelay(1000);
530 else if (err)
531 return -ETIMEDOUT;
532
533 return 0;
534}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100535#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200536
537static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
Andy Fleming272cc702008-10-30 16:41:01 -0500538{
539 int timeout = 1000;
540 int err;
541 struct mmc_cmd cmd;
542
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500543 while (1) {
Andy Fleming272cc702008-10-30 16:41:01 -0500544 cmd.cmdidx = MMC_CMD_APP_CMD;
545 cmd.resp_type = MMC_RSP_R1;
546 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -0500547
548 err = mmc_send_cmd(mmc, &cmd, NULL);
549
550 if (err)
551 return err;
552
553 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
554 cmd.resp_type = MMC_RSP_R3;
Stefano Babic250de122010-01-20 18:20:39 +0100555
556 /*
557 * Most cards do not answer if some reserved bits
558 * in the ocr are set. However, Some controller
559 * can set bit 7 (reserved for low voltages), but
560 * how to manage low voltages SD card is not yet
561 * specified.
562 */
Thomas Choud52ebf12010-12-24 13:12:21 +0000563 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200564 (mmc->cfg->voltages & 0xff8000);
Andy Fleming272cc702008-10-30 16:41:01 -0500565
566 if (mmc->version == SD_VERSION_2)
567 cmd.cmdarg |= OCR_HCS;
568
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200569 if (uhs_en)
570 cmd.cmdarg |= OCR_S18R;
571
Andy Fleming272cc702008-10-30 16:41:01 -0500572 err = mmc_send_cmd(mmc, &cmd, NULL);
573
574 if (err)
575 return err;
576
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500577 if (cmd.response[0] & OCR_BUSY)
578 break;
Andy Fleming272cc702008-10-30 16:41:01 -0500579
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500580 if (timeout-- <= 0)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900581 return -EOPNOTSUPP;
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500582
583 udelay(1000);
584 }
Andy Fleming272cc702008-10-30 16:41:01 -0500585
586 if (mmc->version != SD_VERSION_2)
587 mmc->version = SD_VERSION_1_0;
588
Thomas Choud52ebf12010-12-24 13:12:21 +0000589 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
590 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
591 cmd.resp_type = MMC_RSP_R3;
592 cmd.cmdarg = 0;
Thomas Choud52ebf12010-12-24 13:12:21 +0000593
594 err = mmc_send_cmd(mmc, &cmd, NULL);
595
596 if (err)
597 return err;
598 }
599
Rabin Vincent998be3d2009-04-05 13:30:56 +0530600 mmc->ocr = cmd.response[0];
Andy Fleming272cc702008-10-30 16:41:01 -0500601
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100602#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200603 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
604 == 0x41000000) {
605 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
606 if (err)
607 return err;
608 }
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100609#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200610
Andy Fleming272cc702008-10-30 16:41:01 -0500611 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
612 mmc->rca = 0;
613
614 return 0;
615}
616
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500617static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
Andy Fleming272cc702008-10-30 16:41:01 -0500618{
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500619 struct mmc_cmd cmd;
Andy Fleming272cc702008-10-30 16:41:01 -0500620 int err;
621
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500622 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
623 cmd.resp_type = MMC_RSP_R3;
624 cmd.cmdarg = 0;
Rob Herring5a203972015-03-23 17:56:59 -0500625 if (use_arg && !mmc_host_is_spi(mmc))
626 cmd.cmdarg = OCR_HCS |
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200627 (mmc->cfg->voltages &
Andrew Gabbasova626c8d2015-03-19 07:44:03 -0500628 (mmc->ocr & OCR_VOLTAGE_MASK)) |
629 (mmc->ocr & OCR_ACCESS_MODE);
Che-Liang Chioue9550442012-11-28 15:21:13 +0000630
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500631 err = mmc_send_cmd(mmc, &cmd, NULL);
Che-Liang Chioue9550442012-11-28 15:21:13 +0000632 if (err)
633 return err;
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500634 mmc->ocr = cmd.response[0];
Che-Liang Chioue9550442012-11-28 15:21:13 +0000635 return 0;
636}
637
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200638static int mmc_send_op_cond(struct mmc *mmc)
Che-Liang Chioue9550442012-11-28 15:21:13 +0000639{
Che-Liang Chioue9550442012-11-28 15:21:13 +0000640 int err, i;
641
Andy Fleming272cc702008-10-30 16:41:01 -0500642 /* Some cards seem to need this */
643 mmc_go_idle(mmc);
644
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000645 /* Asking to the card its capabilities */
Che-Liang Chioue9550442012-11-28 15:21:13 +0000646 for (i = 0; i < 2; i++) {
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500647 err = mmc_send_op_cond_iter(mmc, i != 0);
Andy Fleming272cc702008-10-30 16:41:01 -0500648 if (err)
649 return err;
650
Che-Liang Chioue9550442012-11-28 15:21:13 +0000651 /* exit if not busy (flag seems to be inverted) */
Andrew Gabbasova626c8d2015-03-19 07:44:03 -0500652 if (mmc->ocr & OCR_BUSY)
Andrew Gabbasovbd47c132015-03-19 07:44:07 -0500653 break;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000654 }
Andrew Gabbasovbd47c132015-03-19 07:44:07 -0500655 mmc->op_cond_pending = 1;
656 return 0;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000657}
Andy Fleming272cc702008-10-30 16:41:01 -0500658
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200659static int mmc_complete_op_cond(struct mmc *mmc)
Che-Liang Chioue9550442012-11-28 15:21:13 +0000660{
661 struct mmc_cmd cmd;
662 int timeout = 1000;
Vipul Kumar36332b62018-05-03 12:20:54 +0530663 ulong start;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000664 int err;
665
666 mmc->op_cond_pending = 0;
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500667 if (!(mmc->ocr & OCR_BUSY)) {
Yangbo Lud188b112016-08-02 15:33:18 +0800668 /* Some cards seem to need this */
669 mmc_go_idle(mmc);
670
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500671 start = get_timer(0);
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500672 while (1) {
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500673 err = mmc_send_op_cond_iter(mmc, 1);
674 if (err)
675 return err;
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500676 if (mmc->ocr & OCR_BUSY)
677 break;
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500678 if (get_timer(start) > timeout)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900679 return -EOPNOTSUPP;
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500680 udelay(100);
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500681 }
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500682 }
Andy Fleming272cc702008-10-30 16:41:01 -0500683
Thomas Choud52ebf12010-12-24 13:12:21 +0000684 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
685 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
686 cmd.resp_type = MMC_RSP_R3;
687 cmd.cmdarg = 0;
Thomas Choud52ebf12010-12-24 13:12:21 +0000688
689 err = mmc_send_cmd(mmc, &cmd, NULL);
690
691 if (err)
692 return err;
Andrew Gabbasova626c8d2015-03-19 07:44:03 -0500693
694 mmc->ocr = cmd.response[0];
Thomas Choud52ebf12010-12-24 13:12:21 +0000695 }
696
Andy Fleming272cc702008-10-30 16:41:01 -0500697 mmc->version = MMC_VERSION_UNKNOWN;
Andy Fleming272cc702008-10-30 16:41:01 -0500698
699 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
Stephen Warrendef816a2014-01-30 16:11:12 -0700700 mmc->rca = 1;
Andy Fleming272cc702008-10-30 16:41:01 -0500701
702 return 0;
703}
704
705
Kim Phillipsfdbb8732012-10-29 13:34:43 +0000706static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
Andy Fleming272cc702008-10-30 16:41:01 -0500707{
708 struct mmc_cmd cmd;
709 struct mmc_data data;
710 int err;
711
712 /* Get the Card Status Register */
713 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
714 cmd.resp_type = MMC_RSP_R1;
715 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -0500716
Yoshihiro Shimodacdfd1ac2012-06-07 19:09:11 +0000717 data.dest = (char *)ext_csd;
Andy Fleming272cc702008-10-30 16:41:01 -0500718 data.blocks = 1;
Simon Glass8bfa1952013-04-03 08:54:30 +0000719 data.blocksize = MMC_MAX_BLOCK_LEN;
Andy Fleming272cc702008-10-30 16:41:01 -0500720 data.flags = MMC_DATA_READ;
721
722 err = mmc_send_cmd(mmc, &cmd, &data);
723
724 return err;
725}
726
Marek Vasut68925502019-02-06 11:34:27 +0100727static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
728 bool send_status)
Andy Fleming272cc702008-10-30 16:41:01 -0500729{
730 struct mmc_cmd cmd;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000731 int timeout = 1000;
Maxime Riparda9003dc2016-11-04 16:18:08 +0100732 int retries = 3;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000733 int ret;
Andy Fleming272cc702008-10-30 16:41:01 -0500734
735 cmd.cmdidx = MMC_CMD_SWITCH;
736 cmd.resp_type = MMC_RSP_R1b;
737 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000738 (index << 16) |
739 (value << 8);
Andy Fleming272cc702008-10-30 16:41:01 -0500740
Maxime Riparda9003dc2016-11-04 16:18:08 +0100741 while (retries > 0) {
742 ret = mmc_send_cmd(mmc, &cmd, NULL);
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000743
Marek Vasut68925502019-02-06 11:34:27 +0100744 if (ret) {
745 retries--;
746 continue;
Maxime Riparda9003dc2016-11-04 16:18:08 +0100747 }
748
Marek Vasut68925502019-02-06 11:34:27 +0100749 if (!send_status) {
750 mdelay(50);
751 return 0;
752 }
753
754 /* Waiting for the ready status */
755 return mmc_send_status(mmc, timeout);
Maxime Riparda9003dc2016-11-04 16:18:08 +0100756 }
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000757
758 return ret;
759
Andy Fleming272cc702008-10-30 16:41:01 -0500760}
761
Marek Vasut68925502019-02-06 11:34:27 +0100762int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
763{
764 return __mmc_switch(mmc, set, index, value, true);
765}
766
Marek Vasut62d77ce2018-04-15 00:37:11 +0200767#if !CONFIG_IS_ENABLED(MMC_TINY)
Marek Vasutb9a2a0e2019-01-03 21:19:24 +0100768static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
769 bool hsdowngrade)
Andy Fleming272cc702008-10-30 16:41:01 -0500770{
Andy Fleming272cc702008-10-30 16:41:01 -0500771 int err;
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200772 int speed_bits;
773
774 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
775
776 switch (mode) {
777 case MMC_HS:
778 case MMC_HS_52:
779 case MMC_DDR_52:
780 speed_bits = EXT_CSD_TIMING_HS;
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200781 break;
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100782#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200783 case MMC_HS_200:
784 speed_bits = EXT_CSD_TIMING_HS200;
785 break;
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100786#endif
Peng Fan3dd26262018-08-10 14:07:54 +0800787#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
788 case MMC_HS_400:
789 speed_bits = EXT_CSD_TIMING_HS400;
790 break;
791#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200792 case MMC_LEGACY:
793 speed_bits = EXT_CSD_TIMING_LEGACY;
794 break;
795 default:
796 return -EINVAL;
797 }
Marek Vasut68925502019-02-06 11:34:27 +0100798
799 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
800 speed_bits, !hsdowngrade);
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200801 if (err)
802 return err;
803
Marek Vasutb9a2a0e2019-01-03 21:19:24 +0100804#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
805 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
806 /*
807 * In case the eMMC is in HS200/HS400 mode and we are downgrading
808 * to HS mode, the card clock are still running much faster than
809 * the supported HS mode clock, so we can not reliably read out
810 * Extended CSD. Reconfigure the controller to run at HS mode.
811 */
812 if (hsdowngrade) {
813 mmc_select_mode(mmc, MMC_HS);
814 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
815 }
816#endif
817
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200818 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
819 /* Now check to see that it worked */
820 err = mmc_send_ext_csd(mmc, test_csd);
821 if (err)
822 return err;
823
824 /* No high-speed support */
825 if (!test_csd[EXT_CSD_HS_TIMING])
826 return -ENOTSUPP;
827 }
828
829 return 0;
830}
831
832static int mmc_get_capabilities(struct mmc *mmc)
833{
834 u8 *ext_csd = mmc->ext_csd;
835 char cardtype;
Andy Fleming272cc702008-10-30 16:41:01 -0500836
Jean-Jacques Hiblot00e446f2017-11-30 17:43:56 +0100837 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
Andy Fleming272cc702008-10-30 16:41:01 -0500838
Thomas Choud52ebf12010-12-24 13:12:21 +0000839 if (mmc_host_is_spi(mmc))
840 return 0;
841
Andy Fleming272cc702008-10-30 16:41:01 -0500842 /* Only version 4 supports high-speed */
843 if (mmc->version < MMC_VERSION_4)
844 return 0;
845
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200846 if (!ext_csd) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100847 pr_err("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200848 return -ENOTSUPP;
849 }
850
Andrew Gabbasovfc5b32f2014-12-25 10:22:25 -0600851 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
852
Peng Fan3dd26262018-08-10 14:07:54 +0800853 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200854 mmc->cardtype = cardtype;
Andy Fleming272cc702008-10-30 16:41:01 -0500855
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100856#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200857 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
858 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
859 mmc->card_caps |= MMC_MODE_HS200;
860 }
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100861#endif
Peng Fan3dd26262018-08-10 14:07:54 +0800862#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
863 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
864 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
865 mmc->card_caps |= MMC_MODE_HS400;
866 }
867#endif
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900868 if (cardtype & EXT_CSD_CARD_TYPE_52) {
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200869 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900870 mmc->card_caps |= MMC_MODE_DDR_52MHz;
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200871 mmc->card_caps |= MMC_MODE_HS_52MHz;
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900872 }
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200873 if (cardtype & EXT_CSD_CARD_TYPE_26)
874 mmc->card_caps |= MMC_MODE_HS;
Andy Fleming272cc702008-10-30 16:41:01 -0500875
876 return 0;
877}
Marek Vasut62d77ce2018-04-15 00:37:11 +0200878#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500879
Stephen Warrenf866a462013-06-11 15:14:01 -0600880static int mmc_set_capacity(struct mmc *mmc, int part_num)
881{
882 switch (part_num) {
883 case 0:
884 mmc->capacity = mmc->capacity_user;
885 break;
886 case 1:
887 case 2:
888 mmc->capacity = mmc->capacity_boot;
889 break;
890 case 3:
891 mmc->capacity = mmc->capacity_rpmb;
892 break;
893 case 4:
894 case 5:
895 case 6:
896 case 7:
897 mmc->capacity = mmc->capacity_gp[part_num - 4];
898 break;
899 default:
900 return -1;
901 }
902
Simon Glassc40fdca2016-05-01 13:52:35 -0600903 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Stephen Warrenf866a462013-06-11 15:14:01 -0600904
905 return 0;
906}
907
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100908#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200909static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
910{
911 int forbidden = 0;
912 bool change = false;
913
914 if (part_num & PART_ACCESS_MASK)
915 forbidden = MMC_CAP(MMC_HS_200);
916
917 if (MMC_CAP(mmc->selected_mode) & forbidden) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900918 pr_debug("selected mode (%s) is forbidden for part %d\n",
919 mmc_mode_name(mmc->selected_mode), part_num);
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200920 change = true;
921 } else if (mmc->selected_mode != mmc->best_mode) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900922 pr_debug("selected mode is not optimal\n");
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200923 change = true;
924 }
925
926 if (change)
927 return mmc_select_mode_and_width(mmc,
928 mmc->card_caps & ~forbidden);
929
930 return 0;
931}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100932#else
933static inline int mmc_boot_part_access_chk(struct mmc *mmc,
934 unsigned int part_num)
935{
936 return 0;
937}
938#endif
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200939
Simon Glass7dba0b92016-06-12 23:30:15 -0600940int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
Lei Wenbc897b12011-05-02 16:26:26 +0000941{
Stephen Warrenf866a462013-06-11 15:14:01 -0600942 int ret;
Lei Wenbc897b12011-05-02 16:26:26 +0000943
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200944 ret = mmc_boot_part_access_chk(mmc, part_num);
945 if (ret)
946 return ret;
947
Stephen Warrenf866a462013-06-11 15:14:01 -0600948 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
949 (mmc->part_config & ~PART_ACCESS_MASK)
950 | (part_num & PART_ACCESS_MASK));
Stephen Warrenf866a462013-06-11 15:14:01 -0600951
Peter Bigot6dc93e72014-09-02 18:31:23 -0500952 /*
953 * Set the capacity if the switch succeeded or was intended
954 * to return to representing the raw device.
955 */
Stephen Warren873cc1d2015-12-07 11:38:49 -0700956 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
Peter Bigot6dc93e72014-09-02 18:31:23 -0500957 ret = mmc_set_capacity(mmc, part_num);
Simon Glassfdbb1392016-05-01 13:52:37 -0600958 mmc_get_blk_desc(mmc)->hwpart = part_num;
Stephen Warren873cc1d2015-12-07 11:38:49 -0700959 }
Peter Bigot6dc93e72014-09-02 18:31:23 -0500960
961 return ret;
Lei Wenbc897b12011-05-02 16:26:26 +0000962}
963
Jean-Jacques Hiblotcf177892017-11-30 17:44:02 +0100964#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100965int mmc_hwpart_config(struct mmc *mmc,
966 const struct mmc_hwpart_conf *conf,
967 enum mmc_hwpart_conf_mode mode)
968{
969 u8 part_attrs = 0;
970 u32 enh_size_mult;
971 u32 enh_start_addr;
972 u32 gp_size_mult[4];
973 u32 max_enh_size_mult;
974 u32 tot_enh_size_mult = 0;
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100975 u8 wr_rel_set;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100976 int i, pidx, err;
977 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
978
979 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
980 return -EINVAL;
981
982 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100983 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100984 return -EMEDIUMTYPE;
985 }
986
987 if (!(mmc->part_support & PART_SUPPORT)) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100988 pr_err("Card does not support partitioning\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100989 return -EMEDIUMTYPE;
990 }
991
992 if (!mmc->hc_wp_grp_size) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100993 pr_err("Card does not define HC WP group size\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100994 return -EMEDIUMTYPE;
995 }
996
997 /* check partition alignment and total enhanced size */
998 if (conf->user.enh_size) {
999 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1000 conf->user.enh_start % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001001 pr_err("User data enhanced area not HC WP group "
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001002 "size aligned\n");
1003 return -EINVAL;
1004 }
1005 part_attrs |= EXT_CSD_ENH_USR;
1006 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1007 if (mmc->high_capacity) {
1008 enh_start_addr = conf->user.enh_start;
1009 } else {
1010 enh_start_addr = (conf->user.enh_start << 9);
1011 }
1012 } else {
1013 enh_size_mult = 0;
1014 enh_start_addr = 0;
1015 }
1016 tot_enh_size_mult += enh_size_mult;
1017
1018 for (pidx = 0; pidx < 4; pidx++) {
1019 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001020 pr_err("GP%i partition not HC WP group size "
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001021 "aligned\n", pidx+1);
1022 return -EINVAL;
1023 }
1024 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1025 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1026 part_attrs |= EXT_CSD_ENH_GP(pidx);
1027 tot_enh_size_mult += gp_size_mult[pidx];
1028 }
1029 }
1030
1031 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001032 pr_err("Card does not support enhanced attribute\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001033 return -EMEDIUMTYPE;
1034 }
1035
1036 err = mmc_send_ext_csd(mmc, ext_csd);
1037 if (err)
1038 return err;
1039
1040 max_enh_size_mult =
1041 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1042 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1043 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1044 if (tot_enh_size_mult > max_enh_size_mult) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001045 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001046 tot_enh_size_mult, max_enh_size_mult);
1047 return -EMEDIUMTYPE;
1048 }
1049
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +01001050 /* The default value of EXT_CSD_WR_REL_SET is device
1051 * dependent, the values can only be changed if the
1052 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1053 * changed only once and before partitioning is completed. */
1054 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1055 if (conf->user.wr_rel_change) {
1056 if (conf->user.wr_rel_set)
1057 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1058 else
1059 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1060 }
1061 for (pidx = 0; pidx < 4; pidx++) {
1062 if (conf->gp_part[pidx].wr_rel_change) {
1063 if (conf->gp_part[pidx].wr_rel_set)
1064 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1065 else
1066 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1067 }
1068 }
1069
1070 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1071 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1072 puts("Card does not support host controlled partition write "
1073 "reliability settings\n");
1074 return -EMEDIUMTYPE;
1075 }
1076
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001077 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1078 EXT_CSD_PARTITION_SETTING_COMPLETED) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001079 pr_err("Card already partitioned\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001080 return -EPERM;
1081 }
1082
1083 if (mode == MMC_HWPART_CONF_CHECK)
1084 return 0;
1085
1086 /* Partitioning requires high-capacity size definitions */
1087 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1088 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1089 EXT_CSD_ERASE_GROUP_DEF, 1);
1090
1091 if (err)
1092 return err;
1093
1094 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1095
1096 /* update erase group size to be high-capacity */
1097 mmc->erase_grp_size =
1098 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1099
1100 }
1101
1102 /* all OK, write the configuration */
1103 for (i = 0; i < 4; i++) {
1104 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1105 EXT_CSD_ENH_START_ADDR+i,
1106 (enh_start_addr >> (i*8)) & 0xFF);
1107 if (err)
1108 return err;
1109 }
1110 for (i = 0; i < 3; i++) {
1111 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1112 EXT_CSD_ENH_SIZE_MULT+i,
1113 (enh_size_mult >> (i*8)) & 0xFF);
1114 if (err)
1115 return err;
1116 }
1117 for (pidx = 0; pidx < 4; pidx++) {
1118 for (i = 0; i < 3; i++) {
1119 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1120 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1121 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1122 if (err)
1123 return err;
1124 }
1125 }
1126 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1127 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1128 if (err)
1129 return err;
1130
1131 if (mode == MMC_HWPART_CONF_SET)
1132 return 0;
1133
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +01001134 /* The WR_REL_SET is a write-once register but shall be
1135 * written before setting PART_SETTING_COMPLETED. As it is
1136 * write-once we can only write it when completing the
1137 * partitioning. */
1138 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1139 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1140 EXT_CSD_WR_REL_SET, wr_rel_set);
1141 if (err)
1142 return err;
1143 }
1144
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001145 /* Setting PART_SETTING_COMPLETED confirms the partition
1146 * configuration but it only becomes effective after power
1147 * cycle, so we do not adjust the partition related settings
1148 * in the mmc struct. */
1149
1150 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1151 EXT_CSD_PARTITION_SETTING,
1152 EXT_CSD_PARTITION_SETTING_COMPLETED);
1153 if (err)
1154 return err;
1155
1156 return 0;
1157}
Jean-Jacques Hiblotcf177892017-11-30 17:44:02 +01001158#endif
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001159
Simon Glasse7881d82017-07-29 11:35:31 -06001160#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Reding48972d92012-01-02 01:15:37 +00001161int mmc_getcd(struct mmc *mmc)
1162{
1163 int cd;
1164
1165 cd = board_mmc_getcd(mmc);
1166
Peter Korsgaardd4e1da42013-03-21 04:00:03 +00001167 if (cd < 0) {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001168 if (mmc->cfg->ops->getcd)
1169 cd = mmc->cfg->ops->getcd(mmc);
Peter Korsgaardd4e1da42013-03-21 04:00:03 +00001170 else
1171 cd = 1;
1172 }
Thierry Reding48972d92012-01-02 01:15:37 +00001173
1174 return cd;
1175}
Simon Glass8ca51e52016-06-12 23:30:22 -06001176#endif
Thierry Reding48972d92012-01-02 01:15:37 +00001177
Marek Vasut62d77ce2018-04-15 00:37:11 +02001178#if !CONFIG_IS_ENABLED(MMC_TINY)
Kim Phillipsfdbb8732012-10-29 13:34:43 +00001179static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
Andy Fleming272cc702008-10-30 16:41:01 -05001180{
1181 struct mmc_cmd cmd;
1182 struct mmc_data data;
1183
1184 /* Switch the frequency */
1185 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1186 cmd.resp_type = MMC_RSP_R1;
1187 cmd.cmdarg = (mode << 31) | 0xffffff;
1188 cmd.cmdarg &= ~(0xf << (group * 4));
1189 cmd.cmdarg |= value << (group * 4);
Andy Fleming272cc702008-10-30 16:41:01 -05001190
1191 data.dest = (char *)resp;
1192 data.blocksize = 64;
1193 data.blocks = 1;
1194 data.flags = MMC_DATA_READ;
1195
1196 return mmc_send_cmd(mmc, &cmd, &data);
1197}
1198
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001199static int sd_get_capabilities(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05001200{
1201 int err;
1202 struct mmc_cmd cmd;
Suniel Mahesh18e7c8f2017-10-05 11:32:00 +05301203 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1204 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
Andy Fleming272cc702008-10-30 16:41:01 -05001205 struct mmc_data data;
1206 int timeout;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001207#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001208 u32 sd3_bus_mode;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001209#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001210
Jean-Jacques Hiblot00e446f2017-11-30 17:43:56 +01001211 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
Andy Fleming272cc702008-10-30 16:41:01 -05001212
Thomas Choud52ebf12010-12-24 13:12:21 +00001213 if (mmc_host_is_spi(mmc))
1214 return 0;
1215
Andy Fleming272cc702008-10-30 16:41:01 -05001216 /* Read the SCR to find out if this card supports higher speeds */
1217 cmd.cmdidx = MMC_CMD_APP_CMD;
1218 cmd.resp_type = MMC_RSP_R1;
1219 cmd.cmdarg = mmc->rca << 16;
Andy Fleming272cc702008-10-30 16:41:01 -05001220
1221 err = mmc_send_cmd(mmc, &cmd, NULL);
1222
1223 if (err)
1224 return err;
1225
1226 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1227 cmd.resp_type = MMC_RSP_R1;
1228 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -05001229
1230 timeout = 3;
1231
1232retry_scr:
Anton staaff781dd32011-10-03 13:54:59 +00001233 data.dest = (char *)scr;
Andy Fleming272cc702008-10-30 16:41:01 -05001234 data.blocksize = 8;
1235 data.blocks = 1;
1236 data.flags = MMC_DATA_READ;
1237
1238 err = mmc_send_cmd(mmc, &cmd, &data);
1239
1240 if (err) {
1241 if (timeout--)
1242 goto retry_scr;
1243
1244 return err;
1245 }
1246
Yauhen Kharuzhy4e3d89b2009-05-07 00:43:30 +03001247 mmc->scr[0] = __be32_to_cpu(scr[0]);
1248 mmc->scr[1] = __be32_to_cpu(scr[1]);
Andy Fleming272cc702008-10-30 16:41:01 -05001249
1250 switch ((mmc->scr[0] >> 24) & 0xf) {
Bin Meng53e8e402016-03-17 21:53:13 -07001251 case 0:
1252 mmc->version = SD_VERSION_1_0;
1253 break;
1254 case 1:
1255 mmc->version = SD_VERSION_1_10;
1256 break;
1257 case 2:
1258 mmc->version = SD_VERSION_2;
1259 if ((mmc->scr[0] >> 15) & 0x1)
1260 mmc->version = SD_VERSION_3;
1261 break;
1262 default:
1263 mmc->version = SD_VERSION_1_0;
1264 break;
Andy Fleming272cc702008-10-30 16:41:01 -05001265 }
1266
Alagu Sankarb44c7082010-05-12 15:08:24 +05301267 if (mmc->scr[0] & SD_DATA_4BIT)
1268 mmc->card_caps |= MMC_MODE_4BIT;
1269
Andy Fleming272cc702008-10-30 16:41:01 -05001270 /* Version 1.0 doesn't support switching */
1271 if (mmc->version == SD_VERSION_1_0)
1272 return 0;
1273
1274 timeout = 4;
1275 while (timeout--) {
1276 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
Anton staaff781dd32011-10-03 13:54:59 +00001277 (u8 *)switch_status);
Andy Fleming272cc702008-10-30 16:41:01 -05001278
1279 if (err)
1280 return err;
1281
1282 /* The high-speed function is busy. Try again */
Yauhen Kharuzhy4e3d89b2009-05-07 00:43:30 +03001283 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
Andy Fleming272cc702008-10-30 16:41:01 -05001284 break;
1285 }
1286
Andy Fleming272cc702008-10-30 16:41:01 -05001287 /* If high-speed isn't supported, we return */
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001288 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1289 mmc->card_caps |= MMC_CAP(SD_HS);
Andy Fleming272cc702008-10-30 16:41:01 -05001290
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001291#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001292 /* Version before 3.0 don't support UHS modes */
1293 if (mmc->version < SD_VERSION_3)
1294 return 0;
1295
1296 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1297 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1298 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1299 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1300 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1301 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1302 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1303 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1304 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1305 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1306 mmc->card_caps |= MMC_CAP(UHS_DDR50);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001307#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001308
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001309 return 0;
1310}
1311
1312static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1313{
1314 int err;
1315
1316 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001317 int speed;
Macpaul Lin2c3fbf42011-11-28 16:31:09 +00001318
Marek Vasutcf345762018-11-18 03:25:08 +01001319 /* SD version 1.00 and 1.01 does not support CMD 6 */
1320 if (mmc->version == SD_VERSION_1_0)
1321 return 0;
1322
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001323 switch (mode) {
1324 case SD_LEGACY:
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001325 speed = UHS_SDR12_BUS_SPEED;
1326 break;
1327 case SD_HS:
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +01001328 speed = HIGH_SPEED_BUS_SPEED;
1329 break;
1330#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1331 case UHS_SDR12:
1332 speed = UHS_SDR12_BUS_SPEED;
1333 break;
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001334 case UHS_SDR25:
1335 speed = UHS_SDR25_BUS_SPEED;
1336 break;
1337 case UHS_SDR50:
1338 speed = UHS_SDR50_BUS_SPEED;
1339 break;
1340 case UHS_DDR50:
1341 speed = UHS_DDR50_BUS_SPEED;
1342 break;
1343 case UHS_SDR104:
1344 speed = UHS_SDR104_BUS_SPEED;
1345 break;
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +01001346#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001347 default:
1348 return -EINVAL;
1349 }
1350
1351 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
Andy Fleming272cc702008-10-30 16:41:01 -05001352 if (err)
1353 return err;
1354
Jean-Jacques Hiblota0276f32018-02-09 12:09:27 +01001355 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001356 return -ENOTSUPP;
1357
1358 return 0;
1359}
1360
Marek Vasutec360e62018-04-15 00:36:45 +02001361static int sd_select_bus_width(struct mmc *mmc, int w)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001362{
1363 int err;
1364 struct mmc_cmd cmd;
1365
1366 if ((w != 4) && (w != 1))
1367 return -EINVAL;
1368
1369 cmd.cmdidx = MMC_CMD_APP_CMD;
1370 cmd.resp_type = MMC_RSP_R1;
1371 cmd.cmdarg = mmc->rca << 16;
1372
1373 err = mmc_send_cmd(mmc, &cmd, NULL);
1374 if (err)
1375 return err;
1376
1377 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1378 cmd.resp_type = MMC_RSP_R1;
1379 if (w == 4)
1380 cmd.cmdarg = 2;
1381 else if (w == 1)
1382 cmd.cmdarg = 0;
1383 err = mmc_send_cmd(mmc, &cmd, NULL);
1384 if (err)
1385 return err;
Andy Fleming272cc702008-10-30 16:41:01 -05001386
1387 return 0;
1388}
Marek Vasut62d77ce2018-04-15 00:37:11 +02001389#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001390
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001391#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fan3697e592016-09-01 11:13:38 +08001392static int sd_read_ssr(struct mmc *mmc)
1393{
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001394 static const unsigned int sd_au_size[] = {
1395 0, SZ_16K / 512, SZ_32K / 512,
1396 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1397 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1398 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1399 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1400 SZ_64M / 512,
1401 };
Peng Fan3697e592016-09-01 11:13:38 +08001402 int err, i;
1403 struct mmc_cmd cmd;
1404 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1405 struct mmc_data data;
1406 int timeout = 3;
1407 unsigned int au, eo, et, es;
1408
1409 cmd.cmdidx = MMC_CMD_APP_CMD;
1410 cmd.resp_type = MMC_RSP_R1;
1411 cmd.cmdarg = mmc->rca << 16;
1412
1413 err = mmc_send_cmd(mmc, &cmd, NULL);
1414 if (err)
1415 return err;
1416
1417 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1418 cmd.resp_type = MMC_RSP_R1;
1419 cmd.cmdarg = 0;
1420
1421retry_ssr:
1422 data.dest = (char *)ssr;
1423 data.blocksize = 64;
1424 data.blocks = 1;
1425 data.flags = MMC_DATA_READ;
1426
1427 err = mmc_send_cmd(mmc, &cmd, &data);
1428 if (err) {
1429 if (timeout--)
1430 goto retry_ssr;
1431
1432 return err;
1433 }
1434
1435 for (i = 0; i < 16; i++)
1436 ssr[i] = be32_to_cpu(ssr[i]);
1437
1438 au = (ssr[2] >> 12) & 0xF;
1439 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1440 mmc->ssr.au = sd_au_size[au];
1441 es = (ssr[3] >> 24) & 0xFF;
1442 es |= (ssr[2] & 0xFF) << 8;
1443 et = (ssr[3] >> 18) & 0x3F;
1444 if (es && et) {
1445 eo = (ssr[3] >> 16) & 0x3;
1446 mmc->ssr.erase_timeout = (et * 1000) / es;
1447 mmc->ssr.erase_offset = eo * 1000;
1448 }
1449 } else {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001450 pr_debug("Invalid Allocation Unit Size.\n");
Peng Fan3697e592016-09-01 11:13:38 +08001451 }
1452
1453 return 0;
1454}
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001455#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001456/* frequency bases */
1457/* divided by 10 to be nice to platforms without floating point */
Mike Frysinger5f837c22010-10-20 01:15:53 +00001458static const int fbase[] = {
Andy Fleming272cc702008-10-30 16:41:01 -05001459 10000,
1460 100000,
1461 1000000,
1462 10000000,
1463};
1464
1465/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1466 * to platforms without floating point.
1467 */
Simon Glass61fe0762016-05-14 14:02:57 -06001468static const u8 multipliers[] = {
Andy Fleming272cc702008-10-30 16:41:01 -05001469 0, /* reserved */
1470 10,
1471 12,
1472 13,
1473 15,
1474 20,
1475 25,
1476 30,
1477 35,
1478 40,
1479 45,
1480 50,
1481 55,
1482 60,
1483 70,
1484 80,
1485};
1486
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001487static inline int bus_width(uint cap)
1488{
1489 if (cap == MMC_MODE_8BIT)
1490 return 8;
1491 if (cap == MMC_MODE_4BIT)
1492 return 4;
1493 if (cap == MMC_MODE_1BIT)
1494 return 1;
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001495 pr_warn("invalid bus witdh capability 0x%x\n", cap);
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001496 return 0;
1497}
1498
Simon Glasse7881d82017-07-29 11:35:31 -06001499#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001500#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +02001501static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1502{
1503 return -ENOTSUPP;
1504}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001505#endif
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +02001506
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +02001507static void mmc_send_init_stream(struct mmc *mmc)
1508{
1509}
1510
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001511static int mmc_set_ios(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05001512{
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001513 int ret = 0;
1514
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001515 if (mmc->cfg->ops->set_ios)
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001516 ret = mmc->cfg->ops->set_ios(mmc);
1517
1518 return ret;
Andy Fleming272cc702008-10-30 16:41:01 -05001519}
Simon Glass8ca51e52016-06-12 23:30:22 -06001520#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001521
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +02001522int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
Andy Fleming272cc702008-10-30 16:41:01 -05001523{
Jaehoon Chungc0fafe62018-01-23 14:04:30 +09001524 if (!disable) {
Jaehoon Chung9546eb92018-01-17 19:36:58 +09001525 if (clock > mmc->cfg->f_max)
1526 clock = mmc->cfg->f_max;
Andy Fleming272cc702008-10-30 16:41:01 -05001527
Jaehoon Chung9546eb92018-01-17 19:36:58 +09001528 if (clock < mmc->cfg->f_min)
1529 clock = mmc->cfg->f_min;
1530 }
Andy Fleming272cc702008-10-30 16:41:01 -05001531
1532 mmc->clock = clock;
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +02001533 mmc->clk_disable = disable;
Andy Fleming272cc702008-10-30 16:41:01 -05001534
Jaehoon Chungd2faadb2018-01-26 19:25:30 +09001535 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1536
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001537 return mmc_set_ios(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05001538}
1539
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001540static int mmc_set_bus_width(struct mmc *mmc, uint width)
Andy Fleming272cc702008-10-30 16:41:01 -05001541{
1542 mmc->bus_width = width;
1543
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001544 return mmc_set_ios(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05001545}
1546
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001547#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1548/*
1549 * helper function to display the capabilities in a human
1550 * friendly manner. The capabilities include bus width and
1551 * supported modes.
1552 */
1553void mmc_dump_capabilities(const char *text, uint caps)
1554{
1555 enum bus_mode mode;
1556
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001557 pr_debug("%s: widths [", text);
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001558 if (caps & MMC_MODE_8BIT)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001559 pr_debug("8, ");
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001560 if (caps & MMC_MODE_4BIT)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001561 pr_debug("4, ");
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001562 if (caps & MMC_MODE_1BIT)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001563 pr_debug("1, ");
1564 pr_debug("\b\b] modes [");
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001565 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1566 if (MMC_CAP(mode) & caps)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001567 pr_debug("%s, ", mmc_mode_name(mode));
1568 pr_debug("\b\b]\n");
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001569}
1570#endif
1571
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001572struct mode_width_tuning {
1573 enum bus_mode mode;
1574 uint widths;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001575#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001576 uint tuning;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001577#endif
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001578};
1579
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001580#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001581int mmc_voltage_to_mv(enum mmc_voltage voltage)
1582{
1583 switch (voltage) {
1584 case MMC_SIGNAL_VOLTAGE_000: return 0;
1585 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1586 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1587 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1588 }
1589 return -EINVAL;
1590}
1591
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001592static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1593{
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001594 int err;
1595
1596 if (mmc->signal_voltage == signal_voltage)
1597 return 0;
1598
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001599 mmc->signal_voltage = signal_voltage;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001600 err = mmc_set_ios(mmc);
1601 if (err)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001602 pr_debug("unable to set voltage (err %d)\n", err);
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001603
1604 return err;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001605}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001606#else
1607static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1608{
1609 return 0;
1610}
1611#endif
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001612
Marek Vasut62d77ce2018-04-15 00:37:11 +02001613#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001614static const struct mode_width_tuning sd_modes_by_pref[] = {
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001615#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1616#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001617 {
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001618 .mode = UHS_SDR104,
1619 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1620 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1621 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001622#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001623 {
1624 .mode = UHS_SDR50,
1625 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1626 },
1627 {
1628 .mode = UHS_DDR50,
1629 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1630 },
1631 {
1632 .mode = UHS_SDR25,
1633 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1634 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001635#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001636 {
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001637 .mode = SD_HS,
1638 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1639 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001640#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001641 {
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001642 .mode = UHS_SDR12,
1643 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1644 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001645#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001646 {
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001647 .mode = SD_LEGACY,
1648 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1649 }
1650};
1651
1652#define for_each_sd_mode_by_pref(caps, mwt) \
1653 for (mwt = sd_modes_by_pref;\
1654 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1655 mwt++) \
1656 if (caps & MMC_CAP(mwt->mode))
1657
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02001658static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001659{
1660 int err;
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001661 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1662 const struct mode_width_tuning *mwt;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001663#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001664 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001665#else
1666 bool uhs_en = false;
1667#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001668 uint caps;
1669
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001670#ifdef DEBUG
1671 mmc_dump_capabilities("sd card", card_caps);
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001672 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001673#endif
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001674
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001675 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001676 caps = card_caps & mmc->host_caps;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001677
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001678 if (!uhs_en)
1679 caps &= ~UHS_CAPS;
1680
1681 for_each_sd_mode_by_pref(caps, mwt) {
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001682 uint *w;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001683
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001684 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001685 if (*w & caps & mwt->widths) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001686 pr_debug("trying mode %s width %d (at %d MHz)\n",
1687 mmc_mode_name(mwt->mode),
1688 bus_width(*w),
1689 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001690
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001691 /* configure the bus width (card + host) */
1692 err = sd_select_bus_width(mmc, bus_width(*w));
1693 if (err)
1694 goto error;
1695 mmc_set_bus_width(mmc, bus_width(*w));
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001696
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001697 /* configure the bus mode (card) */
1698 err = sd_set_card_speed(mmc, mwt->mode);
1699 if (err)
1700 goto error;
1701
1702 /* configure the bus mode (host) */
1703 mmc_select_mode(mmc, mwt->mode);
Jaehoon Chung65117182018-01-26 19:25:29 +09001704 mmc_set_clock(mmc, mmc->tran_speed,
1705 MMC_CLK_ENABLE);
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001706
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001707#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001708 /* execute tuning if needed */
1709 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1710 err = mmc_execute_tuning(mmc,
1711 mwt->tuning);
1712 if (err) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001713 pr_debug("tuning failed\n");
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001714 goto error;
1715 }
1716 }
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001717#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001718
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001719#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001720 err = sd_read_ssr(mmc);
Peng Fan0a4c2b02018-03-05 16:20:40 +08001721 if (err)
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001722 pr_warn("unable to read ssr\n");
1723#endif
1724 if (!err)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001725 return 0;
1726
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001727error:
1728 /* revert to a safer bus speed */
1729 mmc_select_mode(mmc, SD_LEGACY);
Jaehoon Chung65117182018-01-26 19:25:29 +09001730 mmc_set_clock(mmc, mmc->tran_speed,
1731 MMC_CLK_ENABLE);
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001732 }
1733 }
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001734 }
1735
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001736 pr_err("unable to select a mode\n");
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001737 return -ENOTSUPP;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001738}
1739
Jean-Jacques Hiblot7382e692017-09-21 16:29:52 +02001740/*
1741 * read the compare the part of ext csd that is constant.
1742 * This can be used to check that the transfer is working
1743 * as expected.
1744 */
1745static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1746{
1747 int err;
1748 const u8 *ext_csd = mmc->ext_csd;
1749 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1750
Jean-Jacques Hiblot1de06b92017-11-30 17:43:58 +01001751 if (mmc->version < MMC_VERSION_4)
1752 return 0;
1753
Jean-Jacques Hiblot7382e692017-09-21 16:29:52 +02001754 err = mmc_send_ext_csd(mmc, test_csd);
1755 if (err)
1756 return err;
1757
1758 /* Only compare read only fields */
1759 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1760 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1761 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1762 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1763 ext_csd[EXT_CSD_REV]
1764 == test_csd[EXT_CSD_REV] &&
1765 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1766 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1767 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1768 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1769 return 0;
1770
1771 return -EBADMSG;
1772}
1773
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001774#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001775static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1776 uint32_t allowed_mask)
1777{
1778 u32 card_mask = 0;
1779
1780 switch (mode) {
Peng Fan3dd26262018-08-10 14:07:54 +08001781 case MMC_HS_400:
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001782 case MMC_HS_200:
Peng Fan3dd26262018-08-10 14:07:54 +08001783 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1784 EXT_CSD_CARD_TYPE_HS400_1_8V))
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001785 card_mask |= MMC_SIGNAL_VOLTAGE_180;
Peng Fan3dd26262018-08-10 14:07:54 +08001786 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1787 EXT_CSD_CARD_TYPE_HS400_1_2V))
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001788 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1789 break;
1790 case MMC_DDR_52:
1791 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1792 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1793 MMC_SIGNAL_VOLTAGE_180;
1794 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1795 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1796 break;
1797 default:
1798 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1799 break;
1800 }
1801
1802 while (card_mask & allowed_mask) {
1803 enum mmc_voltage best_match;
1804
1805 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1806 if (!mmc_set_signal_voltage(mmc, best_match))
1807 return 0;
1808
1809 allowed_mask &= ~best_match;
1810 }
1811
1812 return -ENOTSUPP;
1813}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001814#else
1815static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1816 uint32_t allowed_mask)
1817{
1818 return 0;
1819}
1820#endif
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001821
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001822static const struct mode_width_tuning mmc_modes_by_pref[] = {
Peng Fan3dd26262018-08-10 14:07:54 +08001823#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1824 {
1825 .mode = MMC_HS_400,
1826 .widths = MMC_MODE_8BIT,
1827 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1828 },
1829#endif
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001830#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001831 {
1832 .mode = MMC_HS_200,
1833 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001834 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001835 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001836#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001837 {
1838 .mode = MMC_DDR_52,
1839 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1840 },
1841 {
1842 .mode = MMC_HS_52,
1843 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1844 },
1845 {
1846 .mode = MMC_HS,
1847 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1848 },
1849 {
1850 .mode = MMC_LEGACY,
1851 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1852 }
1853};
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001854
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001855#define for_each_mmc_mode_by_pref(caps, mwt) \
1856 for (mwt = mmc_modes_by_pref;\
1857 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1858 mwt++) \
1859 if (caps & MMC_CAP(mwt->mode))
1860
1861static const struct ext_csd_bus_width {
1862 uint cap;
1863 bool is_ddr;
1864 uint ext_csd_bits;
1865} ext_csd_bus_width[] = {
1866 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1867 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1868 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1869 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1870 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1871};
1872
Peng Fan3dd26262018-08-10 14:07:54 +08001873#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1874static int mmc_select_hs400(struct mmc *mmc)
1875{
1876 int err;
1877
1878 /* Set timing to HS200 for tuning */
Marek Vasutb9a2a0e2019-01-03 21:19:24 +01001879 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
Peng Fan3dd26262018-08-10 14:07:54 +08001880 if (err)
1881 return err;
1882
1883 /* configure the bus mode (host) */
1884 mmc_select_mode(mmc, MMC_HS_200);
1885 mmc_set_clock(mmc, mmc->tran_speed, false);
1886
1887 /* execute tuning if needed */
1888 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1889 if (err) {
1890 debug("tuning failed\n");
1891 return err;
1892 }
1893
1894 /* Set back to HS */
BOUGH CHEN5cf12032019-03-26 06:24:17 +00001895 mmc_set_card_speed(mmc, MMC_HS, true);
Peng Fan3dd26262018-08-10 14:07:54 +08001896
1897 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1898 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1899 if (err)
1900 return err;
1901
Marek Vasutb9a2a0e2019-01-03 21:19:24 +01001902 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
Peng Fan3dd26262018-08-10 14:07:54 +08001903 if (err)
1904 return err;
1905
1906 mmc_select_mode(mmc, MMC_HS_400);
1907 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1908 if (err)
1909 return err;
1910
1911 return 0;
1912}
1913#else
1914static int mmc_select_hs400(struct mmc *mmc)
1915{
1916 return -ENOTSUPP;
1917}
1918#endif
1919
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001920#define for_each_supported_width(caps, ddr, ecbv) \
1921 for (ecbv = ext_csd_bus_width;\
1922 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1923 ecbv++) \
1924 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1925
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02001926static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001927{
1928 int err;
1929 const struct mode_width_tuning *mwt;
1930 const struct ext_csd_bus_width *ecbw;
1931
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001932#ifdef DEBUG
1933 mmc_dump_capabilities("mmc", card_caps);
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001934 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001935#endif
1936
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001937 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001938 card_caps &= mmc->host_caps;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001939
1940 /* Only version 4 of MMC supports wider bus widths */
1941 if (mmc->version < MMC_VERSION_4)
1942 return 0;
1943
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02001944 if (!mmc->ext_csd) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001945 pr_debug("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02001946 return -ENOTSUPP;
1947 }
1948
Marek Vasutb9a2a0e2019-01-03 21:19:24 +01001949#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1950 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1951 /*
1952 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
1953 * before doing anything else, since a transition from either of
1954 * the HS200/HS400 mode directly to legacy mode is not supported.
1955 */
1956 if (mmc->selected_mode == MMC_HS_200 ||
1957 mmc->selected_mode == MMC_HS_400)
1958 mmc_set_card_speed(mmc, MMC_HS, true);
1959 else
1960#endif
1961 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02001962
1963 for_each_mmc_mode_by_pref(card_caps, mwt) {
1964 for_each_supported_width(card_caps & mwt->widths,
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001965 mmc_is_mode_ddr(mwt->mode), ecbw) {
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001966 enum mmc_voltage old_voltage;
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001967 pr_debug("trying mode %s width %d (at %d MHz)\n",
1968 mmc_mode_name(mwt->mode),
1969 bus_width(ecbw->cap),
1970 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001971 old_voltage = mmc->signal_voltage;
1972 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1973 MMC_ALL_SIGNAL_VOLTAGE);
1974 if (err)
1975 continue;
1976
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001977 /* configure the bus width (card + host) */
1978 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1979 EXT_CSD_BUS_WIDTH,
1980 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1981 if (err)
1982 goto error;
1983 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1984
Peng Fan3dd26262018-08-10 14:07:54 +08001985 if (mwt->mode == MMC_HS_400) {
1986 err = mmc_select_hs400(mmc);
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001987 if (err) {
Peng Fan3dd26262018-08-10 14:07:54 +08001988 printf("Select HS400 failed %d\n", err);
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001989 goto error;
1990 }
Peng Fan3dd26262018-08-10 14:07:54 +08001991 } else {
1992 /* configure the bus speed (card) */
Marek Vasutb9a2a0e2019-01-03 21:19:24 +01001993 err = mmc_set_card_speed(mmc, mwt->mode, false);
Peng Fan3dd26262018-08-10 14:07:54 +08001994 if (err)
1995 goto error;
1996
1997 /*
1998 * configure the bus width AND the ddr mode
1999 * (card). The host side will be taken care
2000 * of in the next step
2001 */
2002 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2003 err = mmc_switch(mmc,
2004 EXT_CSD_CMD_SET_NORMAL,
2005 EXT_CSD_BUS_WIDTH,
2006 ecbw->ext_csd_bits);
2007 if (err)
2008 goto error;
2009 }
2010
2011 /* configure the bus mode (host) */
2012 mmc_select_mode(mmc, mwt->mode);
2013 mmc_set_clock(mmc, mmc->tran_speed,
2014 MMC_CLK_ENABLE);
2015#ifdef MMC_SUPPORTS_TUNING
2016
2017 /* execute tuning if needed */
2018 if (mwt->tuning) {
2019 err = mmc_execute_tuning(mmc,
2020 mwt->tuning);
2021 if (err) {
2022 pr_debug("tuning failed\n");
2023 goto error;
2024 }
2025 }
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01002026#endif
Peng Fan3dd26262018-08-10 14:07:54 +08002027 }
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02002028
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02002029 /* do a transfer to check the configuration */
2030 err = mmc_read_and_compare_ext_csd(mmc);
2031 if (!err)
2032 return 0;
2033error:
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02002034 mmc_set_signal_voltage(mmc, old_voltage);
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02002035 /* if an error occured, revert to a safer bus mode */
2036 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2037 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2038 mmc_select_mode(mmc, MMC_LEGACY);
2039 mmc_set_bus_width(mmc, 1);
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02002040 }
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02002041 }
2042
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002043 pr_err("unable to select a mode\n");
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02002044
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02002045 return -ENOTSUPP;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02002046}
Marek Vasut62d77ce2018-04-15 00:37:11 +02002047#endif
2048
2049#if CONFIG_IS_ENABLED(MMC_TINY)
2050DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2051#endif
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02002052
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02002053static int mmc_startup_v4(struct mmc *mmc)
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002054{
2055 int err, i;
2056 u64 capacity;
2057 bool has_parts = false;
2058 bool part_completed;
Jean-Jacques Hiblot58a6fb72018-01-04 15:23:31 +01002059 static const u32 mmc_versions[] = {
2060 MMC_VERSION_4,
2061 MMC_VERSION_4_1,
2062 MMC_VERSION_4_2,
2063 MMC_VERSION_4_3,
Jean-Jacques Hiblotace1bed2018-02-09 12:09:28 +01002064 MMC_VERSION_4_4,
Jean-Jacques Hiblot58a6fb72018-01-04 15:23:31 +01002065 MMC_VERSION_4_41,
2066 MMC_VERSION_4_5,
2067 MMC_VERSION_5_0,
2068 MMC_VERSION_5_1
2069 };
2070
Marek Vasut62d77ce2018-04-15 00:37:11 +02002071#if CONFIG_IS_ENABLED(MMC_TINY)
2072 u8 *ext_csd = ext_csd_bkup;
2073
2074 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2075 return 0;
2076
2077 if (!mmc->ext_csd)
2078 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2079
2080 err = mmc_send_ext_csd(mmc, ext_csd);
2081 if (err)
2082 goto error;
2083
2084 /* store the ext csd for future reference */
2085 if (!mmc->ext_csd)
2086 mmc->ext_csd = ext_csd;
2087#else
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002088 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002089
2090 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2091 return 0;
2092
2093 /* check ext_csd version and capacity */
2094 err = mmc_send_ext_csd(mmc, ext_csd);
2095 if (err)
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002096 goto error;
2097
2098 /* store the ext csd for future reference */
2099 if (!mmc->ext_csd)
2100 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2101 if (!mmc->ext_csd)
2102 return -ENOMEM;
2103 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
Marek Vasut62d77ce2018-04-15 00:37:11 +02002104#endif
Alexander Kochetkov76584e32018-02-20 14:35:55 +03002105 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
Jean-Jacques Hiblot58a6fb72018-01-04 15:23:31 +01002106 return -EINVAL;
2107
2108 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2109
2110 if (mmc->version >= MMC_VERSION_4_2) {
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002111 /*
2112 * According to the JEDEC Standard, the value of
2113 * ext_csd's capacity is valid if the value is more
2114 * than 2GB
2115 */
2116 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2117 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2118 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2119 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2120 capacity *= MMC_MAX_BLOCK_LEN;
2121 if ((capacity >> 20) > 2 * 1024)
2122 mmc->capacity_user = capacity;
2123 }
2124
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002125 /* The partition data may be non-zero but it is only
2126 * effective if PARTITION_SETTING_COMPLETED is set in
2127 * EXT_CSD, so ignore any data if this bit is not set,
2128 * except for enabling the high-capacity group size
2129 * definition (see below).
2130 */
2131 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2132 EXT_CSD_PARTITION_SETTING_COMPLETED);
2133
2134 /* store the partition info of emmc */
2135 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2136 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2137 ext_csd[EXT_CSD_BOOT_MULT])
2138 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2139 if (part_completed &&
2140 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2141 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2142
2143 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2144
2145 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2146
2147 for (i = 0; i < 4; i++) {
2148 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2149 uint mult = (ext_csd[idx + 2] << 16) +
2150 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2151 if (mult)
2152 has_parts = true;
2153 if (!part_completed)
2154 continue;
2155 mmc->capacity_gp[i] = mult;
2156 mmc->capacity_gp[i] *=
2157 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2158 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2159 mmc->capacity_gp[i] <<= 19;
2160 }
2161
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +01002162#ifndef CONFIG_SPL_BUILD
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002163 if (part_completed) {
2164 mmc->enh_user_size =
2165 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2166 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2167 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2168 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2169 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2170 mmc->enh_user_size <<= 19;
2171 mmc->enh_user_start =
2172 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2173 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2174 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2175 ext_csd[EXT_CSD_ENH_START_ADDR];
2176 if (mmc->high_capacity)
2177 mmc->enh_user_start <<= 9;
2178 }
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +01002179#endif
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002180
2181 /*
2182 * Host needs to enable ERASE_GRP_DEF bit if device is
2183 * partitioned. This bit will be lost every time after a reset
2184 * or power off. This will affect erase size.
2185 */
2186 if (part_completed)
2187 has_parts = true;
2188 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2189 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2190 has_parts = true;
2191 if (has_parts) {
2192 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2193 EXT_CSD_ERASE_GROUP_DEF, 1);
2194
2195 if (err)
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002196 goto error;
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002197
2198 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2199 }
2200
2201 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002202#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002203 /* Read out group size from ext_csd */
2204 mmc->erase_grp_size =
2205 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002206#endif
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002207 /*
2208 * if high capacity and partition setting completed
2209 * SEC_COUNT is valid even if it is smaller than 2 GiB
2210 * JEDEC Standard JESD84-B45, 6.2.4
2211 */
2212 if (mmc->high_capacity && part_completed) {
2213 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2214 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2215 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2216 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2217 capacity *= MMC_MAX_BLOCK_LEN;
2218 mmc->capacity_user = capacity;
2219 }
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002220 }
2221#if CONFIG_IS_ENABLED(MMC_WRITE)
2222 else {
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002223 /* Calculate the group size from the csd value. */
2224 int erase_gsz, erase_gmul;
2225
2226 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2227 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2228 mmc->erase_grp_size = (erase_gsz + 1)
2229 * (erase_gmul + 1);
2230 }
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002231#endif
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +01002232#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002233 mmc->hc_wp_grp_size = 1024
2234 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2235 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +01002236#endif
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002237
2238 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2239
2240 return 0;
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002241error:
2242 if (mmc->ext_csd) {
Marek Vasut62d77ce2018-04-15 00:37:11 +02002243#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002244 free(mmc->ext_csd);
Marek Vasut62d77ce2018-04-15 00:37:11 +02002245#endif
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002246 mmc->ext_csd = NULL;
2247 }
2248 return err;
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002249}
2250
Kim Phillipsfdbb8732012-10-29 13:34:43 +00002251static int mmc_startup(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05002252{
Stephen Warrenf866a462013-06-11 15:14:01 -06002253 int err, i;
Andy Fleming272cc702008-10-30 16:41:01 -05002254 uint mult, freq;
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002255 u64 cmult, csize;
Andy Fleming272cc702008-10-30 16:41:01 -05002256 struct mmc_cmd cmd;
Simon Glassc40fdca2016-05-01 13:52:35 -06002257 struct blk_desc *bdesc;
Andy Fleming272cc702008-10-30 16:41:01 -05002258
Thomas Choud52ebf12010-12-24 13:12:21 +00002259#ifdef CONFIG_MMC_SPI_CRC_ON
2260 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2261 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2262 cmd.resp_type = MMC_RSP_R1;
2263 cmd.cmdarg = 1;
Thomas Choud52ebf12010-12-24 13:12:21 +00002264 err = mmc_send_cmd(mmc, &cmd, NULL);
Thomas Choud52ebf12010-12-24 13:12:21 +00002265 if (err)
2266 return err;
2267 }
2268#endif
2269
Andy Fleming272cc702008-10-30 16:41:01 -05002270 /* Put the Card in Identify Mode */
Thomas Choud52ebf12010-12-24 13:12:21 +00002271 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2272 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
Andy Fleming272cc702008-10-30 16:41:01 -05002273 cmd.resp_type = MMC_RSP_R2;
2274 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -05002275
2276 err = mmc_send_cmd(mmc, &cmd, NULL);
2277
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +02002278#ifdef CONFIG_MMC_QUIRKS
2279 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2280 int retries = 4;
2281 /*
2282 * It has been seen that SEND_CID may fail on the first
2283 * attempt, let's try a few more time
2284 */
2285 do {
2286 err = mmc_send_cmd(mmc, &cmd, NULL);
2287 if (!err)
2288 break;
2289 } while (retries--);
2290 }
2291#endif
2292
Andy Fleming272cc702008-10-30 16:41:01 -05002293 if (err)
2294 return err;
2295
2296 memcpy(mmc->cid, cmd.response, 16);
2297
2298 /*
2299 * For MMC cards, set the Relative Address.
2300 * For SD cards, get the Relatvie Address.
2301 * This also puts the cards into Standby State
2302 */
Thomas Choud52ebf12010-12-24 13:12:21 +00002303 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2304 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2305 cmd.cmdarg = mmc->rca << 16;
2306 cmd.resp_type = MMC_RSP_R6;
Andy Fleming272cc702008-10-30 16:41:01 -05002307
Thomas Choud52ebf12010-12-24 13:12:21 +00002308 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Fleming272cc702008-10-30 16:41:01 -05002309
Thomas Choud52ebf12010-12-24 13:12:21 +00002310 if (err)
2311 return err;
Andy Fleming272cc702008-10-30 16:41:01 -05002312
Thomas Choud52ebf12010-12-24 13:12:21 +00002313 if (IS_SD(mmc))
2314 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2315 }
Andy Fleming272cc702008-10-30 16:41:01 -05002316
2317 /* Get the Card-Specific Data */
2318 cmd.cmdidx = MMC_CMD_SEND_CSD;
2319 cmd.resp_type = MMC_RSP_R2;
2320 cmd.cmdarg = mmc->rca << 16;
Andy Fleming272cc702008-10-30 16:41:01 -05002321
2322 err = mmc_send_cmd(mmc, &cmd, NULL);
2323
2324 if (err)
2325 return err;
2326
Rabin Vincent998be3d2009-04-05 13:30:56 +05302327 mmc->csd[0] = cmd.response[0];
2328 mmc->csd[1] = cmd.response[1];
2329 mmc->csd[2] = cmd.response[2];
2330 mmc->csd[3] = cmd.response[3];
Andy Fleming272cc702008-10-30 16:41:01 -05002331
2332 if (mmc->version == MMC_VERSION_UNKNOWN) {
Rabin Vincent0b453ff2009-04-05 13:30:55 +05302333 int version = (cmd.response[0] >> 26) & 0xf;
Andy Fleming272cc702008-10-30 16:41:01 -05002334
2335 switch (version) {
Bin Meng53e8e402016-03-17 21:53:13 -07002336 case 0:
2337 mmc->version = MMC_VERSION_1_2;
2338 break;
2339 case 1:
2340 mmc->version = MMC_VERSION_1_4;
2341 break;
2342 case 2:
2343 mmc->version = MMC_VERSION_2_2;
2344 break;
2345 case 3:
2346 mmc->version = MMC_VERSION_3;
2347 break;
2348 case 4:
2349 mmc->version = MMC_VERSION_4;
2350 break;
2351 default:
2352 mmc->version = MMC_VERSION_1_2;
2353 break;
Andy Fleming272cc702008-10-30 16:41:01 -05002354 }
2355 }
2356
2357 /* divide frequency by 10, since the mults are 10x bigger */
Rabin Vincent0b453ff2009-04-05 13:30:55 +05302358 freq = fbase[(cmd.response[0] & 0x7)];
2359 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
Andy Fleming272cc702008-10-30 16:41:01 -05002360
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +02002361 mmc->legacy_speed = freq * mult;
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +02002362 mmc_select_mode(mmc, MMC_LEGACY);
Andy Fleming272cc702008-10-30 16:41:01 -05002363
Markus Niebelab711882013-12-16 13:40:46 +01002364 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
Rabin Vincent998be3d2009-04-05 13:30:56 +05302365 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002366#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Fleming272cc702008-10-30 16:41:01 -05002367
2368 if (IS_SD(mmc))
2369 mmc->write_bl_len = mmc->read_bl_len;
2370 else
Rabin Vincent998be3d2009-04-05 13:30:56 +05302371 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002372#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002373
2374 if (mmc->high_capacity) {
2375 csize = (mmc->csd[1] & 0x3f) << 16
2376 | (mmc->csd[2] & 0xffff0000) >> 16;
2377 cmult = 8;
2378 } else {
2379 csize = (mmc->csd[1] & 0x3ff) << 2
2380 | (mmc->csd[2] & 0xc0000000) >> 30;
2381 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2382 }
2383
Stephen Warrenf866a462013-06-11 15:14:01 -06002384 mmc->capacity_user = (csize + 1) << (cmult + 2);
2385 mmc->capacity_user *= mmc->read_bl_len;
2386 mmc->capacity_boot = 0;
2387 mmc->capacity_rpmb = 0;
2388 for (i = 0; i < 4; i++)
2389 mmc->capacity_gp[i] = 0;
Andy Fleming272cc702008-10-30 16:41:01 -05002390
Simon Glass8bfa1952013-04-03 08:54:30 +00002391 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2392 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Andy Fleming272cc702008-10-30 16:41:01 -05002393
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002394#if CONFIG_IS_ENABLED(MMC_WRITE)
Simon Glass8bfa1952013-04-03 08:54:30 +00002395 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2396 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002397#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002398
Markus Niebelab711882013-12-16 13:40:46 +01002399 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2400 cmd.cmdidx = MMC_CMD_SET_DSR;
2401 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2402 cmd.resp_type = MMC_RSP_NONE;
2403 if (mmc_send_cmd(mmc, &cmd, NULL))
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002404 pr_warn("MMC: SET_DSR failed\n");
Markus Niebelab711882013-12-16 13:40:46 +01002405 }
2406
Andy Fleming272cc702008-10-30 16:41:01 -05002407 /* Select the card, and put it into Transfer Mode */
Thomas Choud52ebf12010-12-24 13:12:21 +00002408 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2409 cmd.cmdidx = MMC_CMD_SELECT_CARD;
Ajay Bhargavfe8f7062011-10-05 03:13:23 +00002410 cmd.resp_type = MMC_RSP_R1;
Thomas Choud52ebf12010-12-24 13:12:21 +00002411 cmd.cmdarg = mmc->rca << 16;
Thomas Choud52ebf12010-12-24 13:12:21 +00002412 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Fleming272cc702008-10-30 16:41:01 -05002413
Thomas Choud52ebf12010-12-24 13:12:21 +00002414 if (err)
2415 return err;
2416 }
Andy Fleming272cc702008-10-30 16:41:01 -05002417
Lei Wene6f99a52011-06-22 17:03:31 +00002418 /*
2419 * For SD, its erase group is always one sector
2420 */
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002421#if CONFIG_IS_ENABLED(MMC_WRITE)
Lei Wene6f99a52011-06-22 17:03:31 +00002422 mmc->erase_grp_size = 1;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002423#endif
Lei Wenbc897b12011-05-02 16:26:26 +00002424 mmc->part_config = MMCPART_NOAVAILABLE;
Lei Wenbc897b12011-05-02 16:26:26 +00002425
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02002426 err = mmc_startup_v4(mmc);
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002427 if (err)
2428 return err;
Sukumar Ghoraid23e2c02010-09-20 18:29:29 +05302429
Simon Glassc40fdca2016-05-01 13:52:35 -06002430 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
Stephen Warrenf866a462013-06-11 15:14:01 -06002431 if (err)
2432 return err;
2433
Marek Vasut62d77ce2018-04-15 00:37:11 +02002434#if CONFIG_IS_ENABLED(MMC_TINY)
2435 mmc_set_clock(mmc, mmc->legacy_speed, false);
2436 mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2437 mmc_set_bus_width(mmc, 1);
2438#else
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02002439 if (IS_SD(mmc)) {
2440 err = sd_get_capabilities(mmc);
2441 if (err)
2442 return err;
2443 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2444 } else {
2445 err = mmc_get_capabilities(mmc);
2446 if (err)
2447 return err;
2448 mmc_select_mode_and_width(mmc, mmc->card_caps);
2449 }
Marek Vasut62d77ce2018-04-15 00:37:11 +02002450#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002451 if (err)
2452 return err;
2453
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02002454 mmc->best_mode = mmc->selected_mode;
Jaehoon Chungad5fd922012-03-26 21:16:03 +00002455
Andrew Gabbasov5af8f452014-12-01 06:59:11 -06002456 /* Fix the block length for DDR mode */
2457 if (mmc->ddr_mode) {
2458 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002459#if CONFIG_IS_ENABLED(MMC_WRITE)
Andrew Gabbasov5af8f452014-12-01 06:59:11 -06002460 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002461#endif
Andrew Gabbasov5af8f452014-12-01 06:59:11 -06002462 }
2463
Andy Fleming272cc702008-10-30 16:41:01 -05002464 /* fill in device description */
Simon Glassc40fdca2016-05-01 13:52:35 -06002465 bdesc = mmc_get_blk_desc(mmc);
2466 bdesc->lun = 0;
2467 bdesc->hwpart = 0;
2468 bdesc->type = 0;
2469 bdesc->blksz = mmc->read_bl_len;
2470 bdesc->log2blksz = LOG2(bdesc->blksz);
2471 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Sjoerd Simonsfc011f62015-12-04 23:27:40 +01002472#if !defined(CONFIG_SPL_BUILD) || \
2473 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2474 !defined(CONFIG_USE_TINY_PRINTF))
Simon Glassc40fdca2016-05-01 13:52:35 -06002475 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
Taylor Huttbabce5f2012-10-20 17:15:59 +00002476 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2477 (mmc->cid[3] >> 16) & 0xffff);
Simon Glassc40fdca2016-05-01 13:52:35 -06002478 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
Taylor Huttbabce5f2012-10-20 17:15:59 +00002479 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2480 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2481 (mmc->cid[2] >> 24) & 0xff);
Simon Glassc40fdca2016-05-01 13:52:35 -06002482 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
Taylor Huttbabce5f2012-10-20 17:15:59 +00002483 (mmc->cid[2] >> 16) & 0xf);
Paul Burton56196822013-09-04 16:12:25 +01002484#else
Simon Glassc40fdca2016-05-01 13:52:35 -06002485 bdesc->vendor[0] = 0;
2486 bdesc->product[0] = 0;
2487 bdesc->revision[0] = 0;
Paul Burton56196822013-09-04 16:12:25 +01002488#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002489
Andre Przywaraeef05fd2018-12-17 10:05:45 +00002490#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2491 part_init(bdesc);
2492#endif
2493
Andy Fleming272cc702008-10-30 16:41:01 -05002494 return 0;
2495}
2496
Kim Phillipsfdbb8732012-10-29 13:34:43 +00002497static int mmc_send_if_cond(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05002498{
2499 struct mmc_cmd cmd;
2500 int err;
2501
2502 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2503 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02002504 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
Andy Fleming272cc702008-10-30 16:41:01 -05002505 cmd.resp_type = MMC_RSP_R7;
Andy Fleming272cc702008-10-30 16:41:01 -05002506
2507 err = mmc_send_cmd(mmc, &cmd, NULL);
2508
2509 if (err)
2510 return err;
2511
Rabin Vincent998be3d2009-04-05 13:30:56 +05302512 if ((cmd.response[0] & 0xff) != 0xaa)
Jaehoon Chung915ffa52016-07-19 16:33:36 +09002513 return -EOPNOTSUPP;
Andy Fleming272cc702008-10-30 16:41:01 -05002514 else
2515 mmc->version = SD_VERSION_2;
2516
2517 return 0;
2518}
2519
Simon Glassc4d660d2017-07-04 13:31:19 -06002520#if !CONFIG_IS_ENABLED(DM_MMC)
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +01002521/* board-specific MMC power initializations. */
2522__weak void board_mmc_power_init(void)
2523{
2524}
Simon Glass05cbeb72017-04-22 19:10:56 -06002525#endif
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +01002526
Peng Fan2051aef2016-10-11 15:08:43 +08002527static int mmc_power_init(struct mmc *mmc)
2528{
Simon Glassc4d660d2017-07-04 13:31:19 -06002529#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +02002530#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan2051aef2016-10-11 15:08:43 +08002531 int ret;
2532
2533 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +02002534 &mmc->vmmc_supply);
2535 if (ret)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002536 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
Peng Fan2051aef2016-10-11 15:08:43 +08002537
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +02002538 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2539 &mmc->vqmmc_supply);
2540 if (ret)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002541 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
Peng Fan2051aef2016-10-11 15:08:43 +08002542#endif
Simon Glass05cbeb72017-04-22 19:10:56 -06002543#else /* !CONFIG_DM_MMC */
2544 /*
2545 * Driver model should use a regulator, as above, rather than calling
2546 * out to board code.
2547 */
2548 board_mmc_power_init();
2549#endif
Peng Fan2051aef2016-10-11 15:08:43 +08002550 return 0;
2551}
2552
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002553/*
2554 * put the host in the initial state:
2555 * - turn on Vdd (card power supply)
2556 * - configure the bus width and clock to minimal values
2557 */
2558static void mmc_set_initial_state(struct mmc *mmc)
2559{
2560 int err;
2561
2562 /* First try to set 3.3V. If it fails set to 1.8V */
2563 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2564 if (err != 0)
2565 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2566 if (err != 0)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002567 pr_warn("mmc: failed to set signal voltage\n");
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002568
2569 mmc_select_mode(mmc, MMC_LEGACY);
2570 mmc_set_bus_width(mmc, 1);
Jaehoon Chung65117182018-01-26 19:25:29 +09002571 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002572}
2573
2574static int mmc_power_on(struct mmc *mmc)
2575{
2576#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2577 if (mmc->vmmc_supply) {
2578 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2579
2580 if (ret) {
2581 puts("Error enabling VMMC supply\n");
2582 return ret;
2583 }
2584 }
2585#endif
2586 return 0;
2587}
2588
2589static int mmc_power_off(struct mmc *mmc)
2590{
Jaehoon Chung65117182018-01-26 19:25:29 +09002591 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002592#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2593 if (mmc->vmmc_supply) {
2594 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2595
2596 if (ret) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002597 pr_debug("Error disabling VMMC supply\n");
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002598 return ret;
2599 }
2600 }
2601#endif
2602 return 0;
2603}
2604
2605static int mmc_power_cycle(struct mmc *mmc)
2606{
2607 int ret;
2608
2609 ret = mmc_power_off(mmc);
2610 if (ret)
2611 return ret;
2612 /*
2613 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2614 * to be on the safer side.
2615 */
2616 udelay(2000);
2617 return mmc_power_on(mmc);
2618}
2619
Jon Nettleton6c09eba2018-06-11 15:26:19 +03002620int mmc_get_op_cond(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05002621{
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02002622 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
Macpaul Linafd59322011-11-14 23:35:39 +00002623 int err;
Andy Fleming272cc702008-10-30 16:41:01 -05002624
Lei Wenbc897b12011-05-02 16:26:26 +00002625 if (mmc->has_init)
2626 return 0;
2627
Yangbo Lu5a8dbdc2015-04-22 13:57:00 +08002628#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2629 mmc_adapter_card_type_ident();
2630#endif
Peng Fan2051aef2016-10-11 15:08:43 +08002631 err = mmc_power_init(mmc);
2632 if (err)
2633 return err;
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +01002634
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +02002635#ifdef CONFIG_MMC_QUIRKS
2636 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2637 MMC_QUIRK_RETRY_SEND_CID;
2638#endif
2639
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +02002640 err = mmc_power_cycle(mmc);
2641 if (err) {
2642 /*
2643 * if power cycling is not supported, we should not try
2644 * to use the UHS modes, because we wouldn't be able to
2645 * recover from an error during the UHS initialization.
2646 */
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002647 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +02002648 uhs_en = false;
2649 mmc->host_caps &= ~UHS_CAPS;
2650 err = mmc_power_on(mmc);
2651 }
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002652 if (err)
2653 return err;
2654
Simon Glasse7881d82017-07-29 11:35:31 -06002655#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass8ca51e52016-06-12 23:30:22 -06002656 /* The device has already been probed ready for use */
2657#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +02002658 /* made sure it's not NULL earlier */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02002659 err = mmc->cfg->ops->init(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05002660 if (err)
2661 return err;
Simon Glass8ca51e52016-06-12 23:30:22 -06002662#endif
Andrew Gabbasov786e8f82014-12-01 06:59:09 -06002663 mmc->ddr_mode = 0;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02002664
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02002665retry:
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002666 mmc_set_initial_state(mmc);
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +02002667 mmc_send_init_stream(mmc);
2668
Andy Fleming272cc702008-10-30 16:41:01 -05002669 /* Reset the Card */
2670 err = mmc_go_idle(mmc);
2671
2672 if (err)
2673 return err;
2674
Lei Wenbc897b12011-05-02 16:26:26 +00002675 /* The internal partition reset to user partition(0) at every CMD0*/
Simon Glassc40fdca2016-05-01 13:52:35 -06002676 mmc_get_blk_desc(mmc)->hwpart = 0;
Lei Wenbc897b12011-05-02 16:26:26 +00002677
Andy Fleming272cc702008-10-30 16:41:01 -05002678 /* Test for SD version 2 */
Macpaul Linafd59322011-11-14 23:35:39 +00002679 err = mmc_send_if_cond(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05002680
Andy Fleming272cc702008-10-30 16:41:01 -05002681 /* Now try to get the SD card's operating condition */
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02002682 err = sd_send_op_cond(mmc, uhs_en);
2683 if (err && uhs_en) {
2684 uhs_en = false;
2685 mmc_power_cycle(mmc);
2686 goto retry;
2687 }
Andy Fleming272cc702008-10-30 16:41:01 -05002688
2689 /* If the command timed out, we check for an MMC card */
Jaehoon Chung915ffa52016-07-19 16:33:36 +09002690 if (err == -ETIMEDOUT) {
Andy Fleming272cc702008-10-30 16:41:01 -05002691 err = mmc_send_op_cond(mmc);
2692
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002693 if (err) {
Paul Burton56196822013-09-04 16:12:25 +01002694#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002695 pr_err("Card did not respond to voltage select!\n");
Paul Burton56196822013-09-04 16:12:25 +01002696#endif
Jaehoon Chung915ffa52016-07-19 16:33:36 +09002697 return -EOPNOTSUPP;
Andy Fleming272cc702008-10-30 16:41:01 -05002698 }
2699 }
2700
Jon Nettleton6c09eba2018-06-11 15:26:19 +03002701 return err;
2702}
2703
2704int mmc_start_init(struct mmc *mmc)
2705{
2706 bool no_card;
2707 int err = 0;
2708
2709 /*
2710 * all hosts are capable of 1 bit bus-width and able to use the legacy
2711 * timings.
2712 */
2713 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2714 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2715
2716#if !defined(CONFIG_MMC_BROKEN_CD)
2717 /* we pretend there's no card when init is NULL */
2718 no_card = mmc_getcd(mmc) == 0;
2719#else
2720 no_card = 0;
2721#endif
2722#if !CONFIG_IS_ENABLED(DM_MMC)
2723 no_card = no_card || (mmc->cfg->ops->init == NULL);
2724#endif
2725 if (no_card) {
2726 mmc->has_init = 0;
2727#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2728 pr_err("MMC: no card present\n");
2729#endif
2730 return -ENOMEDIUM;
2731 }
2732
2733 err = mmc_get_op_cond(mmc);
2734
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002735 if (!err)
Che-Liang Chioue9550442012-11-28 15:21:13 +00002736 mmc->init_in_progress = 1;
2737
2738 return err;
2739}
2740
2741static int mmc_complete_init(struct mmc *mmc)
2742{
2743 int err = 0;
2744
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002745 mmc->init_in_progress = 0;
Che-Liang Chioue9550442012-11-28 15:21:13 +00002746 if (mmc->op_cond_pending)
2747 err = mmc_complete_op_cond(mmc);
2748
2749 if (!err)
2750 err = mmc_startup(mmc);
Lei Wenbc897b12011-05-02 16:26:26 +00002751 if (err)
2752 mmc->has_init = 0;
2753 else
2754 mmc->has_init = 1;
Che-Liang Chioue9550442012-11-28 15:21:13 +00002755 return err;
2756}
2757
2758int mmc_init(struct mmc *mmc)
2759{
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002760 int err = 0;
Vipul Kumar36332b62018-05-03 12:20:54 +05302761 __maybe_unused ulong start;
Simon Glassc4d660d2017-07-04 13:31:19 -06002762#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass33fb2112016-05-01 13:52:41 -06002763 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
Che-Liang Chioue9550442012-11-28 15:21:13 +00002764
Simon Glass33fb2112016-05-01 13:52:41 -06002765 upriv->mmc = mmc;
2766#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +00002767 if (mmc->has_init)
2768 return 0;
Mateusz Zalegad803fea2014-04-29 20:15:30 +02002769
2770 start = get_timer(0);
2771
Che-Liang Chioue9550442012-11-28 15:21:13 +00002772 if (!mmc->init_in_progress)
2773 err = mmc_start_init(mmc);
2774
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002775 if (!err)
Che-Liang Chioue9550442012-11-28 15:21:13 +00002776 err = mmc_complete_init(mmc);
Jagan Teki919b4852017-01-10 11:18:43 +01002777 if (err)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002778 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
Jagan Teki919b4852017-01-10 11:18:43 +01002779
Lei Wenbc897b12011-05-02 16:26:26 +00002780 return err;
Andy Fleming272cc702008-10-30 16:41:01 -05002781}
2782
Marek Vasutfceea992019-01-29 04:45:51 +01002783#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2784 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2785 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2786int mmc_deinit(struct mmc *mmc)
2787{
2788 u32 caps_filtered;
2789
2790 if (!mmc->has_init)
2791 return 0;
2792
2793 if (IS_SD(mmc)) {
2794 caps_filtered = mmc->card_caps &
2795 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2796 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2797 MMC_CAP(UHS_SDR104));
2798
2799 return sd_select_mode_and_width(mmc, caps_filtered);
2800 } else {
2801 caps_filtered = mmc->card_caps &
2802 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2803
2804 return mmc_select_mode_and_width(mmc, caps_filtered);
2805 }
2806}
2807#endif
2808
Markus Niebelab711882013-12-16 13:40:46 +01002809int mmc_set_dsr(struct mmc *mmc, u16 val)
2810{
2811 mmc->dsr = val;
2812 return 0;
2813}
2814
Jeroen Hofsteecee9ab72014-07-10 22:46:28 +02002815/* CPU-specific MMC initializations */
2816__weak int cpu_mmc_init(bd_t *bis)
Andy Fleming272cc702008-10-30 16:41:01 -05002817{
2818 return -1;
2819}
2820
Jeroen Hofsteecee9ab72014-07-10 22:46:28 +02002821/* board-specific MMC initializations. */
2822__weak int board_mmc_init(bd_t *bis)
2823{
2824 return -1;
2825}
Andy Fleming272cc702008-10-30 16:41:01 -05002826
Che-Liang Chioue9550442012-11-28 15:21:13 +00002827void mmc_set_preinit(struct mmc *mmc, int preinit)
2828{
2829 mmc->preinit = preinit;
2830}
2831
Faiz Abbas8a856db2018-02-12 19:35:24 +05302832#if CONFIG_IS_ENABLED(DM_MMC)
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002833static int mmc_probe(bd_t *bis)
2834{
Simon Glass4a1db6d2015-12-29 05:22:49 -07002835 int ret, i;
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002836 struct uclass *uc;
Simon Glass4a1db6d2015-12-29 05:22:49 -07002837 struct udevice *dev;
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002838
2839 ret = uclass_get(UCLASS_MMC, &uc);
2840 if (ret)
2841 return ret;
2842
Simon Glass4a1db6d2015-12-29 05:22:49 -07002843 /*
2844 * Try to add them in sequence order. Really with driver model we
2845 * should allow holes, but the current MMC list does not allow that.
2846 * So if we request 0, 1, 3 we will get 0, 1, 2.
2847 */
2848 for (i = 0; ; i++) {
2849 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2850 if (ret == -ENODEV)
2851 break;
2852 }
2853 uclass_foreach_dev(dev, uc) {
2854 ret = device_probe(dev);
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002855 if (ret)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002856 pr_err("%s - probe failed: %d\n", dev->name, ret);
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002857 }
2858
2859 return 0;
2860}
2861#else
2862static int mmc_probe(bd_t *bis)
2863{
2864 if (board_mmc_init(bis) < 0)
2865 cpu_mmc_init(bis);
2866
2867 return 0;
2868}
2869#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +00002870
Andy Fleming272cc702008-10-30 16:41:01 -05002871int mmc_initialize(bd_t *bis)
2872{
Daniel Kochmański1b26bab2015-05-29 16:55:43 +02002873 static int initialized = 0;
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002874 int ret;
Daniel Kochmański1b26bab2015-05-29 16:55:43 +02002875 if (initialized) /* Avoid initializing mmc multiple times */
2876 return 0;
2877 initialized = 1;
2878
Simon Glassc4d660d2017-07-04 13:31:19 -06002879#if !CONFIG_IS_ENABLED(BLK)
Marek Vasutb5b838f2016-12-01 02:06:33 +01002880#if !CONFIG_IS_ENABLED(MMC_TINY)
Simon Glassc40fdca2016-05-01 13:52:35 -06002881 mmc_list_init();
2882#endif
Marek Vasutb5b838f2016-12-01 02:06:33 +01002883#endif
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002884 ret = mmc_probe(bis);
2885 if (ret)
2886 return ret;
Andy Fleming272cc702008-10-30 16:41:01 -05002887
Ying Zhangbb0dc102013-08-16 15:16:11 +08002888#ifndef CONFIG_SPL_BUILD
Andy Fleming272cc702008-10-30 16:41:01 -05002889 print_mmc_devices(',');
Ying Zhangbb0dc102013-08-16 15:16:11 +08002890#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002891
Simon Glassc40fdca2016-05-01 13:52:35 -06002892 mmc_do_preinit();
Andy Fleming272cc702008-10-30 16:41:01 -05002893 return 0;
2894}
Tomas Melincd3d4882016-11-25 11:01:03 +02002895
2896#ifdef CONFIG_CMD_BKOPS_ENABLE
2897int mmc_set_bkops_enable(struct mmc *mmc)
2898{
2899 int err;
2900 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2901
2902 err = mmc_send_ext_csd(mmc, ext_csd);
2903 if (err) {
2904 puts("Could not get ext_csd register values\n");
2905 return err;
2906 }
2907
2908 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2909 puts("Background operations not supported on device\n");
2910 return -EMEDIUMTYPE;
2911 }
2912
2913 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2914 puts("Background operations already enabled\n");
2915 return 0;
2916 }
2917
2918 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2919 if (err) {
2920 puts("Failed to enable manual background operations\n");
2921 return err;
2922 }
2923
2924 puts("Enabled manual background operations\n");
2925
2926 return 0;
2927}
2928#endif