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Siva Durga Prasad Paladugu04ab29a2018-04-11 14:13:05 +05301// SPDX-License-Identifier: GPL-2.0
2/*
Michal Simek420d4462019-05-21 12:07:23 +02003 * dts file for Xilinx ZynqMP ZCU1275 RevB
Siva Durga Prasad Paladugu04ab29a2018-04-11 14:13:05 +05304 *
5 * (C) Copyright 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15
16/ {
Michal Simek420d4462019-05-21 12:07:23 +020017 model = "ZynqMP ZCU1275 RevB";
18 compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
19 "xlnx,zynqmp";
Siva Durga Prasad Paladugu04ab29a2018-04-11 14:13:05 +053020
21 aliases {
22 serial0 = &uart0;
23 serial1 = &dcc;
24 spi0 = &qspi;
25 mmc0 = &sdhci1;
26 };
27
28 chosen {
29 bootargs = "earlycon";
30 stdout-path = "serial0:115200n8";
31 };
32
33 memory@0 {
34 device_type = "memory";
35 reg = <0x0 0x0 0x0 0x80000000>;
36 };
37};
38
39&dcc {
40 status = "okay";
41};
42
43&qspi {
44 status = "okay";
45 flash@0 {
Neil Armstrongffd4c7c2019-02-10 10:16:20 +000046 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Siva Durga Prasad Paladugu04ab29a2018-04-11 14:13:05 +053047 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0x0>;
50 spi-tx-bus-width = <1>;
Venkatesh Yadav Abbarapu053d4bd2018-11-14 17:20:18 +053051 spi-rx-bus-width = <1>;
Siva Durga Prasad Paladugu04ab29a2018-04-11 14:13:05 +053052 spi-max-frequency = <108000000>; /* Based on DC1 spec */
53 partition@qspi-fsbl-uboot { /* for testing purpose */
54 label = "qspi-fsbl-uboot";
55 reg = <0x0 0x100000>;
56 };
57 partition@qspi-linux { /* for testing purpose */
58 label = "qspi-linux";
59 reg = <0x100000 0x500000>;
60 };
61 partition@qspi-device-tree { /* for testing purpose */
62 label = "qspi-device-tree";
63 reg = <0x600000 0x20000>;
64 };
65 partition@qspi-rootfs { /* for testing purpose */
66 label = "qspi-rootfs";
67 reg = <0x620000 0x5E0000>;
68 };
69 };
70};
71
72&uart0 {
73 status = "okay";
74};
75
76&sdhci1 {
77 status = "okay";
78 no-1-8-v;
79 xlnx,mio_bank = <1>;
80};