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wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * MPC8560 FCC Fast Ethernet
3 * Copyright (c) 2003 Motorola,Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
7 *
8 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * MPC8560 FCC Fast Ethernet
32 * Basic ET HW initialization and packet RX/TX routines
33 *
34 * This code will not perform the IO port configuration. This should be
35 * done in the iop_conf_t structure specific for the board.
36 *
37 * TODO:
38 * add a PHY driver to do the negotiation
39 * reflect negotiation results in FPSMR
40 * look for ways to configure the board specific stuff elsewhere, eg.
41 * config_xxx.h or the board directory
42 */
43
44#include <common.h>
45#include <malloc.h>
46#include <asm/cpm_85xx.h>
47#include <command.h>
48#include <config.h>
49#include <net.h>
50
51#if defined(CONFIG_MPC8560)
52
53#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
54 defined(CONFIG_NET_MULTI)
55
56static struct ether_fcc_info_s
57{
58 int ether_index;
59 int proff_enet;
60 ulong cpm_cr_enet_sblock;
61 ulong cpm_cr_enet_page;
62 ulong cmxfcr_mask;
63 ulong cmxfcr_value;
64}
65 ether_fcc_info[] =
66{
67#ifdef CONFIG_ETHER_ON_FCC1
68{
69 0,
70 PROFF_FCC1,
71 CPM_CR_FCC1_SBLOCK,
72 CPM_CR_FCC1_PAGE,
73 CFG_CMXFCR_MASK1,
74 CFG_CMXFCR_VALUE1
75},
76#endif
77
78#ifdef CONFIG_ETHER_ON_FCC2
79{
80 1,
81 PROFF_FCC2,
82 CPM_CR_FCC2_SBLOCK,
83 CPM_CR_FCC2_PAGE,
84 CFG_CMXFCR_MASK2,
85 CFG_CMXFCR_VALUE2
86},
87#endif
88
89#ifdef CONFIG_ETHER_ON_FCC3
90{
91 2,
92 PROFF_FCC3,
93 CPM_CR_FCC3_SBLOCK,
94 CPM_CR_FCC3_PAGE,
95 CFG_CMXFCR_MASK3,
96 CFG_CMXFCR_VALUE3
97},
98#endif
99};
100
101/*---------------------------------------------------------------------*/
102
103/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
104#define PKT_MAXDMA_SIZE 1520
105
106/* The FCC stores dest/src/type, data, and checksum for receive packets. */
107#define PKT_MAXBUF_SIZE 1518
108#define PKT_MINBUF_SIZE 64
109
110/* Maximum input buffer size. Must be a multiple of 32. */
111#define PKT_MAXBLR_SIZE 1536
112
113#define TOUT_LOOP 1000000
114
115#define TX_BUF_CNT 2
116
117static uint rxIdx; /* index of the current RX buffer */
118static uint txIdx; /* index of the current TX buffer */
119
120/*
121 * FCC Ethernet Tx and Rx buffer descriptors.
122 * Provide for Double Buffering
123 * Note: PKTBUFSRX is defined in net.h
124 */
125
126typedef volatile struct rtxbd {
127 cbd_t rxbd[PKTBUFSRX];
128 cbd_t txbd[TX_BUF_CNT];
129} RTXBD;
130
131/* Good news: the FCC supports external BDs! */
132#ifdef __GNUC__
133static RTXBD rtx __attribute__ ((aligned(8)));
134#else
135#error "rtx must be 64-bit aligned"
136#endif
137
138#define ET_DEBUG
139
140static int fec_send(struct eth_device* dev, volatile void *packet, int length)
141{
142 int i = 0;
143 int result = 0;
144
145 if (length <= 0) {
146 printf("fec: bad packet size: %d\n", length);
147 goto out;
148 }
149
150 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
151 if (i >= TOUT_LOOP) {
152 printf("fec: tx buffer not ready\n");
153 goto out;
154 }
155 }
156
157 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
158 rtx.txbd[txIdx].cbd_datlen = length;
159 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
160 BD_ENET_TX_TC );
161
162 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
163 if (i >= TOUT_LOOP) {
164 printf("fec: tx error\n");
165 goto out;
166 }
167 }
168
169#ifdef ET_DEBUG
170 printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
171 printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
172 for(i=0;i<(length/16 + 1);i++) {
173 printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
174 *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
175 *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
176 }
177#endif
178
179 /* return only status bits */
180 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
181 txIdx = (txIdx + 1) % TX_BUF_CNT;
182
183out:
184 return result;
185}
186
187static int fec_recv(struct eth_device* dev)
188{
189 int length;
190
191 for (;;)
192 {
193 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
194 length = -1;
195 break; /* nothing received - leave for() loop */
196 }
197 length = rtx.rxbd[rxIdx].cbd_datlen;
198
199 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
200 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
201 }
202 else {
203 /* Pass the packet up to the protocol layers. */
204 NetReceive(NetRxPackets[rxIdx], length - 4);
205 }
206
207
208 /* Give the buffer back to the FCC. */
209 rtx.rxbd[rxIdx].cbd_datlen = 0;
210
211 /* wrap around buffer index when necessary */
212 if ((rxIdx + 1) >= PKTBUFSRX) {
213 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
214 rxIdx = 0;
215 }
216 else {
217 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
218 rxIdx++;
219 }
220 }
221 return length;
222}
223
224
225static int fec_init(struct eth_device* dev, bd_t *bis)
226{
227 struct ether_fcc_info_s * info = dev->priv;
228 int i;
229 volatile immap_t *immr = (immap_t *)CFG_IMMR;
230 volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
231 fcc_enet_t *pram_ptr;
232 unsigned long mem_addr;
233
234#if 0
235 mii_discover_phy();
236#endif
237
238 /* 28.9 - (1-2): ioports have been set up already */
239
240 /* 28.9 - (3): connect FCC's tx and rx clocks */
241 immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
242 immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
243 info->cmxfcr_value;
244
245 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
246 if(info->ether_index == 0) {
247 immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
248 } else if (info->ether_index == 1) {
249 immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
250 } else if (info->ether_index == 2) {
251 immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
252 }
253
254 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
255 if(info->ether_index == 0) {
256 immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
257 } else if (info->ether_index == 1){
258 immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
259 } else if (info->ether_index == 2){
260 immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
261 }
262
263 /* 28.9 - (6): FDSR: Ethernet Syn */
264 if(info->ether_index == 0) {
265 immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
266 } else if (info->ether_index == 1) {
267 immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
268 } else if (info->ether_index == 2) {
269 immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
270 }
271
272 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
273 rxIdx = 0;
274 txIdx = 0;
275
276 /* Setup Receiver Buffer Descriptors */
277 for (i = 0; i < PKTBUFSRX; i++)
278 {
279 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
280 rtx.rxbd[i].cbd_datlen = 0;
281 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
282 }
283 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
284
285 /* Setup Ethernet Transmitter Buffer Descriptors */
286 for (i = 0; i < TX_BUF_CNT; i++)
287 {
288 rtx.txbd[i].cbd_sc = 0;
289 rtx.txbd[i].cbd_datlen = 0;
290 rtx.txbd[i].cbd_bufaddr = 0;
291 }
292 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
293
294 /* 28.9 - (7): initialize parameter ram */
295 pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
296
297 /* clear whole structure to make sure all reserved fields are zero */
298 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
299
300 /*
301 * common Parameter RAM area
302 *
303 * Allocate space in the reserved FCC area of DPRAM for the
304 * internal buffers. No one uses this space (yet), so we
305 * can do this. Later, we will add resource management for
306 * this area. CPM_FCC_SPECIAL_BASE: 0xb000.
307 */
308 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
309 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
310 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
311 /*
312 * Set maximum bytes per receive buffer.
313 * It must be a multiple of 32.
314 */
315 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
316 /* localbus SDRAM should be preferred */
317 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
318 CFG_CPMFCR_RAMTYPE) << 24;
319 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
320 pram_ptr->fen_genfcc.fcc_rbdstat = 0;
321 pram_ptr->fen_genfcc.fcc_rbdlen = 0;
322 pram_ptr->fen_genfcc.fcc_rdptr = 0;
323 /* localbus SDRAM should be preferred */
324 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
325 CFG_CPMFCR_RAMTYPE) << 24;
326 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
327 pram_ptr->fen_genfcc.fcc_tbdstat = 0;
328 pram_ptr->fen_genfcc.fcc_tbdlen = 0;
329 pram_ptr->fen_genfcc.fcc_tdptr = 0;
330
331 /* protocol-specific area */
332 pram_ptr->fen_statbuf = 0x0;
333 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
334 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
335 pram_ptr->fen_crcec = 0;
336 pram_ptr->fen_alec = 0;
337 pram_ptr->fen_disfc = 0;
338 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
339 pram_ptr->fen_retcnt = 0;
340 pram_ptr->fen_pper = 0;
341 pram_ptr->fen_boffcnt = 0;
342 pram_ptr->fen_gaddrh = 0;
343 pram_ptr->fen_gaddrl = 0;
344 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
345 /*
346 * Set Ethernet station address.
347 *
348 * This is supplied in the board information structure, so we
349 * copy that into the controller.
350 * So far we have only been given one Ethernet address. We make
351 * it unique by setting a few bits in the upper byte of the
352 * non-static part of the address.
353 */
354#define ea eth_get_dev()->enetaddr
355 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
356 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
357 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
358#undef ea
359 pram_ptr->fen_ibdcount = 0;
360 pram_ptr->fen_ibdstart = 0;
361 pram_ptr->fen_ibdend = 0;
362 pram_ptr->fen_txlen = 0;
363 pram_ptr->fen_iaddrh = 0; /* disable hash */
364 pram_ptr->fen_iaddrl = 0;
365 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
366 /* pad pointer. use tiptr since we don't need a specific padding char */
367 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
368 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
369 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
370
371#if defined(ET_DEBUG)
372 printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
373 printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
374 pram_ptr->fen_genfcc.fcc_rbase);
375 printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
376 pram_ptr->fen_genfcc.fcc_tbase);
377#endif
378
379 /* 28.9 - (8)(9): clear out events in FCCE */
380 /* 28.9 - (9): FCCM: mask all events */
381 if(info->ether_index == 0) {
382 immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
383 immr->im_cpm.im_cpm_fcc1.fccm = 0;
384 } else if (info->ether_index == 1) {
385 immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
386 immr->im_cpm.im_cpm_fcc2.fccm = 0;
387 } else if (info->ether_index == 2) {
388 immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
389 immr->im_cpm.im_cpm_fcc3.fccm = 0;
390 }
391
392 /* 28.9 - (10-12): we don't use ethernet interrupts */
393
394 /* 28.9 - (13)
395 *
396 * Let's re-initialize the channel now. We have to do it later
397 * than the manual describes because we have just now finished
398 * the BD initialization.
399 */
400 cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
401 info->cpm_cr_enet_sblock,
402 0x0c,
403 CPM_CR_INIT_TRX) | CPM_CR_FLG;
404 do {
405 __asm__ __volatile__ ("eieio");
406 } while (cp->cpcr & CPM_CR_FLG);
407
408 /* 28.9 - (14): enable tx/rx in gfmr */
409 if(info->ether_index == 0) {
410 immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
411 } else if (info->ether_index == 1) {
412 immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
413 } else if (info->ether_index == 2) {
414 immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
415 }
416
417 return 0;
418}
419
420static void fec_halt(struct eth_device* dev)
421{
422 struct ether_fcc_info_s * info = dev->priv;
423 volatile immap_t *immr = (immap_t *)CFG_IMMR;
424
425 /* write GFMR: disable tx/rx */
426 if(info->ether_index == 0) {
427 immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
428 } else if(info->ether_index == 1) {
429 immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
430 } else if(info->ether_index == 2) {
431 immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
432 }
433}
434
435int fec_initialize(bd_t *bis)
436{
437 struct eth_device* dev;
438 int i;
439
440 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
441 {
442 dev = (struct eth_device*) malloc(sizeof *dev);
443 memset(dev, 0, sizeof *dev);
444
445 sprintf(dev->name, "FCC%d ETHERNET",
446 ether_fcc_info[i].ether_index + 1);
447 dev->priv = &ether_fcc_info[i];
448 dev->init = fec_init;
449 dev->halt = fec_halt;
450 dev->send = fec_send;
451 dev->recv = fec_recv;
452
453 eth_register(dev);
454 }
455
456 return 1;
457}
458
459#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
460
461#endif /* CONFIG_MPC8560 */