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gerrit.cesnet.cz / github / trini / u-boot / 5b72dbfc23e4f9a62cfe787816c5b5e75a0aa597 / . / drivers / net / ax88796.h
blob: 2b4e05af3bf3de799e12fa7d066de02b9a443a8f [file] [log] [blame]
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]1/*
2 * AX88796L(NE2000) support
3 *
4 * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]7 */
8
9#ifndef __DRIVERS_AX88796L_H__
10#define __DRIVERS_AX88796L_H__
11
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]12#define DP_DATA (0x10 << 1)
13#define START_PG 0x40 /* First page of TX buffer */
14#define START_PG2 0x48
15#define STOP_PG 0x80 /* Last page +1 of RX ring */
16#define TX_PAGES 12
17#define RX_START (START_PG+TX_PAGES)
18#define RX_END STOP_PG
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]19
20#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]21#define AX88796L_BYTE_ACCESS 0x00001000
22#define AX88796L_OFFSET 0x00000400
23#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]24 AX88796L_BYTE_ACCESS + AX88796L_OFFSET
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]25#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1)
26#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1)
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]27
28#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR))
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]29#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR))
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]30
31#define EECS_HIGH (AX88796L_MEMR |= 0x10)
32#define EECS_LOW (AX88796L_MEMR &= 0xef)
33#define EECLK_HIGH (AX88796L_MEMR |= 0x80)
34#define EECLK_LOW (AX88796L_MEMR &= 0x7f)
35#define EEDI_HIGH (AX88796L_MEMR |= 0x20)
36#define EEDI_LOW (AX88796L_MEMR &= 0xdf)
37#define EEDO ((AX88796L_MEMR & 0x40)>>6)
38
39#define PAGE0_SET (AX88796L_CR &= 0x3f)
40#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
41
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]42#define BIT_DUMMY 0
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]43#define MAC_EEP_READ 1
44#define MAC_EEP_WRITE 2
45#define MAC_EEP_ERACE 3
46#define MAC_EEP_EWEN 4
47#define MAC_EEP_EWDS 5
48
49/* R7780MP Specific code */
50#if defined(CONFIG_R7780MP)
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]51#define ISA_OFFSET 0x1400
52#define DP_IN(_b_, _o_, _d_) (_d_) = \
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]53 *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
54#define DP_OUT(_b_, _o_, _d_) \
55 *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]56#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
57#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]58#else
59/* Please change for your target boards */
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]60#define ISA_OFFSET 0x0000
61#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
62#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
63#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
64#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]65#endif
66
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]67#endif /* __DRIVERS_AX88796L_H__ */