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Jagan Teki0d47bc72018-12-22 21:32:49 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
Samuel Holland21d314a2021-09-12 11:48:43 -05007#ifndef _CLK_SUNXI_H
8#define _CLK_SUNXI_H
Jagan Teki0d47bc72018-12-22 21:32:49 +05309
Simon Glasscd93d622020-05-10 11:40:13 -060010#include <linux/bitops.h>
Simon Glasscd93d622020-05-10 11:40:13 -060011
Jagan Teki0d47bc72018-12-22 21:32:49 +053012/**
Jagan Teki99ba4302019-01-18 22:18:13 +053013 * enum ccu_flags - ccu clock/reset flags
Jagan Teki0d47bc72018-12-22 21:32:49 +053014 *
15 * @CCU_CLK_F_IS_VALID: is given clock gate is valid?
Jagan Teki99ba4302019-01-18 22:18:13 +053016 * @CCU_RST_F_IS_VALID: is given reset control is valid?
Jagan Teki0d47bc72018-12-22 21:32:49 +053017 */
18enum ccu_flags {
19 CCU_CLK_F_IS_VALID = BIT(0),
Jagan Teki99ba4302019-01-18 22:18:13 +053020 CCU_RST_F_IS_VALID = BIT(1),
Andre Przywarad6cb09d2022-05-05 01:25:43 +010021 CCU_CLK_F_DUMMY_GATE = BIT(2),
Jagan Teki0d47bc72018-12-22 21:32:49 +053022};
23
24/**
25 * struct ccu_clk_gate - ccu clock gate
26 * @off: gate offset
27 * @bit: gate bit
28 * @flags: ccu clock gate flags
29 */
30struct ccu_clk_gate {
31 u16 off;
32 u32 bit;
33 enum ccu_flags flags;
34};
35
36#define GATE(_off, _bit) { \
37 .off = _off, \
38 .bit = _bit, \
39 .flags = CCU_CLK_F_IS_VALID, \
40}
41
Andre Przywarad6cb09d2022-05-05 01:25:43 +010042#define GATE_DUMMY { \
43 .flags = CCU_CLK_F_DUMMY_GATE, \
44}
45
Jagan Teki0d47bc72018-12-22 21:32:49 +053046/**
Jagan Teki99ba4302019-01-18 22:18:13 +053047 * struct ccu_reset - ccu reset
48 * @off: reset offset
49 * @bit: reset bit
50 * @flags: ccu reset control flags
51 */
52struct ccu_reset {
53 u16 off;
54 u32 bit;
55 enum ccu_flags flags;
56};
57
58#define RESET(_off, _bit) { \
59 .off = _off, \
60 .bit = _bit, \
61 .flags = CCU_RST_F_IS_VALID, \
62}
63
64/**
Jagan Teki0d47bc72018-12-22 21:32:49 +053065 * struct ccu_desc - clock control unit descriptor
66 *
67 * @gates: clock gates
Jagan Teki99ba4302019-01-18 22:18:13 +053068 * @resets: reset unit
Jagan Teki0d47bc72018-12-22 21:32:49 +053069 */
70struct ccu_desc {
71 const struct ccu_clk_gate *gates;
Jagan Teki99ba4302019-01-18 22:18:13 +053072 const struct ccu_reset *resets;
Samuel Holland49b2b0a2022-05-09 00:29:31 -050073 u8 num_gates;
74 u8 num_resets;
Jagan Teki0d47bc72018-12-22 21:32:49 +053075};
76
77/**
Samuel Holland5af97b62022-05-09 00:29:35 -050078 * struct ccu_plat - sunxi clock control unit platform data
Jagan Teki0d47bc72018-12-22 21:32:49 +053079 *
80 * @base: base address
81 * @desc: ccu descriptor
82 */
Samuel Holland5af97b62022-05-09 00:29:35 -050083struct ccu_plat {
Jagan Teki0d47bc72018-12-22 21:32:49 +053084 void *base;
85 const struct ccu_desc *desc;
86};
87
Jagan Teki0d47bc72018-12-22 21:32:49 +053088extern struct clk_ops sunxi_clk_ops;
89
Jagan Teki99ba4302019-01-18 22:18:13 +053090/**
91 * sunxi_reset_bind() - reset binding
92 *
93 * @dev: reset device
Heinrich Schuchardt185f8122022-01-19 18:05:50 +010094 * Return: 0 success, or error value
Jagan Teki99ba4302019-01-18 22:18:13 +053095 */
Samuel Hollandd39088a2022-05-09 00:29:33 -050096int sunxi_reset_bind(struct udevice *dev);
Jagan Teki99ba4302019-01-18 22:18:13 +053097
Samuel Holland21d314a2021-09-12 11:48:43 -050098#endif /* _CLK_SUNXI_H */