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Stefano Babic8be4f402016-06-06 11:19:42 +02001/*
2 * Copyright (C) Stefano Babic <sbabic@denx.de>
3 *
4 * Configuration settings for the E+L i.MX6Q DO82 board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __EL6Q_COMMON_CONFIG_H
10#define __EL6Q_COMMON_CONFIG_H
11
12#define CONFIG_BOARD_NAME EL6Q
13
14#include <config_distro_defaults.h>
15#include "mx6_common.h"
16
17#define CONFIG_IMX_THERMAL
18
19/* Size of malloc() pool */
20#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
21
22#define CONFIG_BOARD_EARLY_INIT_F
23#define CONFIG_BOARD_LATE_INIT
24
25#define CONFIG_MXC_UART
26
27#ifdef CONFIG_SPL
Stefano Babic8be4f402016-06-06 11:19:42 +020028#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
29#define CONFIG_SPL_SPI_LOAD
30#include "imx6_spl.h"
31#endif
32
33/* MMC Configs */
34#define CONFIG_SYS_FSL_ESDHC_ADDR 0
35#define CONFIG_SYS_FSL_USDHC_NUM 2
36
37/* I2C config */
38#define CONFIG_SYS_I2C
39#define CONFIG_SYS_I2C_MXC
40#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
41#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
42#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
43#define CONFIG_SYS_I2C_SPEED 100000
44
45/* PMIC */
46#define CONFIG_POWER
47#define CONFIG_POWER_I2C
48#define CONFIG_POWER_PFUZE100
49#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
50
51/* Commands */
52#define CONFIG_MXC_SPI
53#define CONFIG_SF_DEFAULT_BUS 3
54#define CONFIG_SF_DEFAULT_CS 0
55#define CONFIG_SF_DEFAULT_SPEED 20000000
56#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
57
58/* allow to overwrite serial and ethaddr */
59#define CONFIG_ENV_OVERWRITE
60#define CONFIG_MXC_UART_BASE UART2_BASE
61#define CONFIG_BAUDRATE 115200
62
63/* Command definition */
64
65#define CONFIG_CMD_BMODE
66#define CONFIG_CMD_BOOTZ
67#undef CONFIG_CMD_IMLS
68
69#define CONFIG_BOARD_NAME EL6Q
70
71#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
72#define CONFIG_EXTRA_ENV_SETTINGS \
73 "board="__stringify(CONFIG_BOARD_NAME)"\0" \
74 "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \
75 "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \
Simon Glass12ca05a2016-10-17 20:12:39 -060076 "console=" CONSOLE_DEV "\0" \
Stefano Babic8be4f402016-06-06 11:19:42 +020077 "fdtfile=undefined\0" \
78 "fdt_high=0xffffffff\0" \
79 "fdt_addr_r=0x18000000\0" \
80 "fdt_addr=0x18000000\0" \
81 "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \
82 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
83 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
84 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
85 BOOTENV
86
87#define BOOT_TARGET_DEVICES(func) \
88 func(MMC, mmc, 0) \
89 func(MMC, mmc, 1) \
90 func(PXE, PXE, na) \
91 func(DHCP, dhcp, na)
92
93#define CONFIG_BOOTCOMMAND \
94 "run findfdt; " \
95 "run distro_bootcmd"
96
97#include <config_distro_bootcmd.h>
98
99#define CONFIG_ARP_TIMEOUT 200UL
100
101#define CONFIG_CMD_MEMTEST
102
103#define CONFIG_SYS_MEMTEST_START 0x10000000
104#define CONFIG_SYS_MEMTEST_END 0x10800000
105#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
106
107#define CONFIG_STACKSIZE (128 * 1024)
108
109/* Physical Memory Map */
110#define CONFIG_NR_DRAM_BANKS 1
111#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
112
113#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
114#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
115#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
116
117#define CONFIG_SYS_INIT_SP_OFFSET \
118 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
119#define CONFIG_SYS_INIT_SP_ADDR \
120 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
121
122/* FLASH and environment organization */
123#define CONFIG_SYS_NO_FLASH
124
125#define CONFIG_ENV_SIZE (8 * 1024)
126
127#define CONFIG_ENV_IS_IN_MMC
128
129#if defined(CONFIG_ENV_IS_IN_MMC)
130#define CONFIG_SYS_MMC_ENV_DEV 1
131#define CONFIG_SYS_MMC_ENV_PART 2
132#define CONFIG_ENV_OFFSET 0x0
133#endif
134
135#endif /* __EL6Q_COMMON_CONFIG_H */