wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com |
| 4 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | /* |
| 16 | * High Level Configuration Options |
| 17 | * (easy to change) |
| 18 | */ |
| 19 | |
| 20 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ |
| 21 | #define CONFIG_4xx 1 /* ...member of PPC405 family */ |
| 22 | #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ |
| 23 | #define CONFIG_W7OLMG 1 /* ...specifically an LMG */ |
| 24 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 25 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
| 26 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 27 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 28 | #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ |
Peter Tyser | 3a8f28d | 2009-09-16 22:03:07 -0500 | [diff] [blame] | 29 | #define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 30 | |
| 31 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
| 32 | |
| 33 | #define CONFIG_BAUDRATE 9600 |
| 34 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
| 35 | |
| 36 | #if 1 |
| 37 | #define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ |
| 38 | #else |
| 39 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
| 40 | #endif |
| 41 | |
| 42 | #undef CONFIG_BOOTARGS |
| 43 | |
| 44 | #define CONFIG_LOADADDR F0080000 |
| 45 | |
| 46 | #define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ |
| 47 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
| 48 | #define CONFIG_IPADDR 192.168.1.1 |
| 49 | #define CONFIG_NETMASK 255.255.255.0 |
| 50 | #define CONFIG_SERVERIP 192.168.1.2 |
| 51 | |
| 52 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 53 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 54 | |
Ben Warren | 96e21f8 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 55 | #define CONFIG_PPC4xx_EMAC |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 56 | #define CONFIG_MII 1 /* MII PHY management */ |
| 57 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
| 58 | |
| 59 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ |
| 60 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
| 61 | #define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 62 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
| 63 | #define CONFIG_SYS_DTT_LOW_TEMP -30 |
| 64 | #define CONFIG_SYS_DTT_HYSTERESIS 3 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 65 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 66 | |
Jon Loeliger | a556290 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 67 | /* |
Jon Loeliger | a1aa0bb | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 68 | * BOOTP options |
| 69 | */ |
| 70 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 71 | #define CONFIG_BOOTP_BOOTPATH |
| 72 | #define CONFIG_BOOTP_GATEWAY |
| 73 | #define CONFIG_BOOTP_HOSTNAME |
| 74 | |
| 75 | |
| 76 | /* |
Jon Loeliger | a556290 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 77 | * Command line configuration. |
| 78 | */ |
| 79 | #include <config_cmd_default.h> |
| 80 | |
| 81 | #define CONFIG_CMD_PCI |
| 82 | #define CONFIG_CMD_IRQ |
| 83 | #define CONFIG_CMD_ASKENV |
| 84 | #define CONFIG_CMD_DHCP |
| 85 | #define CONFIG_CMD_BEDBUG |
| 86 | #define CONFIG_CMD_DATE |
| 87 | #define CONFIG_CMD_I2C |
| 88 | #define CONFIG_CMD_EEPROM |
| 89 | #define CONFIG_CMD_ELF |
| 90 | #define CONFIG_CMD_BSP |
| 91 | #define CONFIG_CMD_REGINFO |
| 92 | #define CONFIG_CMD_DTT |
| 93 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 94 | |
| 95 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 96 | #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ |
| 97 | |
| 98 | #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 99 | #define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 100 | /* |
| 101 | * Miscellaneous configurable options |
| 102 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 104 | #define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ |
| 105 | #undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */ |
| 106 | #ifdef CONFIG_SYS_HUSH_PARSER |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 107 | #endif |
Jon Loeliger | a556290 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 108 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 110 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 112 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 114 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 115 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 116 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 117 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 118 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 119 | |
Stefan Roese | 550650d | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 120 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 121 | #define CONFIG_SYS_NS16550 |
| 122 | #define CONFIG_SYS_NS16550_SERIAL |
| 123 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 124 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
| 127 | #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
| 128 | #define CONFIG_SYS_BASE_BAUD 384000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 129 | |
| 130 | |
| 131 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_BAUDRATE_TABLE {9600} |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 135 | #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 136 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 137 | /*----------------------------------------------------------------------- |
| 138 | * PCI stuff |
| 139 | *----------------------------------------------------------------------- |
| 140 | */ |
| 141 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
| 142 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 143 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
| 144 | |
| 145 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 146 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 147 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
| 148 | #define CONFIG_PCI_PNP /* pci plug-and-play */ |
| 149 | /* resource configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ |
| 151 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ |
| 152 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| 153 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
| 154 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 155 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ |
| 156 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ |
| 157 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 158 | |
| 159 | /*----------------------------------------------------------------------- |
| 160 | * Set up values for external bus controller |
| 161 | * used by cpu_init.c |
| 162 | *----------------------------------------------------------------------- |
| 163 | */ |
| 164 | /* use PerWE instead of PCI_INT ( these functions share a pin ) */ |
| 165 | #define CONFIG_USE_PERWE 1 |
| 166 | |
| 167 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 169 | |
| 170 | /* bank 0 is boot flash */ |
| 171 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 173 | /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | #define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 175 | |
| 176 | /* bank 1 is main flash */ |
| 177 | /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_EBC_PB1AP 0x04850240 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 179 | /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | #define CONFIG_SYS_EBC_PB1CR 0xF00FC000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 181 | |
| 182 | /* bank 2 is RTC/NVRAM */ |
| 183 | /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #define CONFIG_SYS_EBC_PB2AP 0x03000440 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 185 | /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_EBC_PB2CR 0xFC018000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 187 | |
| 188 | /* bank 3 is FPGA 0 */ |
| 189 | /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_EBC_PB3AP 0x02000400 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 191 | /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_EBC_PB3CR 0xFD01A000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 193 | |
| 194 | /* bank 4 is SAM 8 bit range */ |
| 195 | /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #define CONFIG_SYS_EBC_PB4AP 0x02840380 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 197 | /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | #define CONFIG_SYS_EBC_PB4CR 0xFE878000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 199 | |
| 200 | /* bank 5 is SAM 16 bit range */ |
| 201 | /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_EBC_PB5AP 0x05040d80 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 203 | /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 204 | #define CONFIG_SYS_EBC_PB5CR 0xFD87A000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 205 | |
| 206 | /* bank 6 is unused */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 207 | /* PB6AP = 0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 208 | #define CONFIG_SYS_EBC_PB6AP 0x00000000 |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 209 | /* PB6CR = 0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 210 | #define CONFIG_SYS_EBC_PB6CR 0x00000000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 211 | |
| 212 | /* bank 7 is LED register */ |
| 213 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | #define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 215 | /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | #define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 217 | |
| 218 | /*----------------------------------------------------------------------- |
| 219 | * Start addresses for the final memory configuration |
| 220 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 221 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 222 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 224 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 |
| 225 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 226 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */ |
| 227 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 228 | |
| 229 | /* |
| 230 | * For booting Linux, the board info and command line data |
| 231 | * have to be in the first 8 MB of memory, since this is |
| 232 | * the maximum mapped by the Linux kernel during initialization. |
| 233 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 235 | /*----------------------------------------------------------------------- |
| 236 | * FLASH organization |
| 237 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 238 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 239 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 240 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 241 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ |
| 242 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ |
| 243 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 244 | |
| 245 | #if 1 /* Use NVRAM for environment variables */ |
| 246 | /*----------------------------------------------------------------------- |
| 247 | * NVRAM organization |
| 248 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 9314cee | 2008-09-10 22:47:59 +0200 | [diff] [blame] | 249 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 250 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ |
| 251 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 252 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
| 253 | /*define CONFIG_ENV_ADDR \ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 254 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */ |
| 255 | #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 256 | |
| 257 | #else /* Use Boot Flash for environment variables */ |
| 258 | /*----------------------------------------------------------------------- |
| 259 | * Flash EEPROM for environment |
| 260 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 261 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 262 | #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
| 263 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 264 | |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 265 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 266 | #endif |
| 267 | |
| 268 | /*----------------------------------------------------------------------- |
| 269 | * I2C EEPROM (ATMEL 24C04N) |
| 270 | */ |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 271 | #define CONFIG_SYS_I2C |
| 272 | #define CONFIG_SYS_I2C_PPC4XX |
| 273 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| 274 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
| 275 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 276 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 277 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ |
| 278 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
| 279 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 280 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 281 | /*----------------------------------------------------------------------- |
| 282 | * Definitions for Serial Presence Detect EEPROM address |
| 283 | * (to get SDRAM settings) |
| 284 | */ |
| 285 | #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ |
| 286 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 287 | /* |
| 288 | * Init Memory Controller: |
| 289 | */ |
| 290 | #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ |
| 291 | #define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ |
| 292 | |
| 293 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 294 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 295 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 296 | |
| 297 | /*----------------------------------------------------------------------- |
| 298 | * Definitions for initial stack pointer and data area (in RAM) |
| 299 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 300 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 301 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 302 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 303 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 304 | |
Jon Loeliger | a556290 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 305 | #if defined(CONFIG_CMD_KGDB) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 306 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 307 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 308 | #endif |
| 309 | |
| 310 | /* |
| 311 | * FPGA(s) configuration |
| 312 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 313 | #define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 314 | #define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ |
| 315 | #define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ |
| 316 | #define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ |
| 317 | #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ |
| 318 | |
| 319 | #endif /* __CONFIG_H */ |