blob: 8469afdaae9da8d18e046218a354eb789b87ddd5 [file] [log] [blame]
Minkyu Kangdd2c9e62009-10-01 17:20:28 +09001/*
2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Heungjun Kim <riverful.kim@samsung.com>
5 *
6 * based on drivers/serial/s3c64xx.c
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Minkyu Kangdd2c9e62009-10-01 17:20:28 +09009 */
10
11#include <common.h>
Simon Glass73e256c2014-09-14 16:36:17 -060012#include <dm.h>
13#include <errno.h>
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +053014#include <fdtdec.h>
Mike Frysinger6c768ca2011-04-29 18:03:29 +000015#include <linux/compiler.h>
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090016#include <asm/io.h>
17#include <asm/arch/uart.h>
18#include <asm/arch/clk.h>
19#include <serial.h>
20
John Rigby29565322010-12-20 18:27:51 -070021DECLARE_GLOBAL_DATA_PTR;
22
Simon Glass73e256c2014-09-14 16:36:17 -060023#define RX_FIFO_COUNT_SHIFT 0
24#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
25#define RX_FIFO_FULL (1 << 8)
26#define TX_FIFO_COUNT_SHIFT 16
27#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
28#define TX_FIFO_FULL (1 << 24)
Akshay Saraswatffbff1d2013-03-21 20:33:04 +000029
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +053030/* Information about a serial port */
Simon Glass73e256c2014-09-14 16:36:17 -060031struct s5p_serial_platdata {
32 struct s5p_uart *reg; /* address of registers in physical memory */
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +053033 u8 port_id; /* uart port number */
Simon Glass73e256c2014-09-14 16:36:17 -060034};
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090035
36/*
Minkyu Kang46a3b5c2010-03-24 16:59:30 +090037 * The coefficient, used to calculate the baudrate on S5P UARTs is
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090038 * calculated as
39 * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
40 * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
41 * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
42 */
43static const int udivslot[] = {
44 0,
45 0x0080,
46 0x0808,
47 0x0888,
48 0x2222,
49 0x4924,
50 0x4a52,
51 0x54aa,
52 0x5555,
53 0xd555,
54 0xd5d5,
55 0xddd5,
56 0xdddd,
57 0xdfdd,
58 0xdfdf,
59 0xffdf,
60};
61
Simon Glass73e256c2014-09-14 16:36:17 -060062int s5p_serial_setbrg(struct udevice *dev, int baudrate)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090063{
Simon Glass73e256c2014-09-14 16:36:17 -060064 struct s5p_serial_platdata *plat = dev->platdata;
65 struct s5p_uart *const uart = plat->reg;
66 u32 uclk = get_uart_clk(plat->port_id);
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090067 u32 val;
68
Minkyu Kangf70409a2010-08-24 15:51:55 +090069 val = uclk / baudrate;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090070
71 writel(val / 16 - 1, &uart->ubrdiv);
Minkyu Kang1628cfc2010-09-28 14:35:02 +090072
Minkyu Kange0617c62011-01-24 14:43:25 +090073 if (s5p_uart_divslot())
Minkyu Kang1628cfc2010-09-28 14:35:02 +090074 writew(udivslot[val % 16], &uart->rest.slot);
75 else
76 writeb(val % 16, &uart->rest.value);
Simon Glass73e256c2014-09-14 16:36:17 -060077
78 return 0;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090079}
80
Simon Glass73e256c2014-09-14 16:36:17 -060081static int s5p_serial_probe(struct udevice *dev)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090082{
Simon Glass73e256c2014-09-14 16:36:17 -060083 struct s5p_serial_platdata *plat = dev->platdata;
84 struct s5p_uart *const uart = plat->reg;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090085
Inha Songe6252fa2014-02-04 14:57:25 +090086 /* enable FIFOs, auto clear Rx FIFO */
87 writel(0x3, &uart->ufcon);
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090088 writel(0, &uart->umcon);
89 /* 8N1 */
90 writel(0x3, &uart->ulcon);
91 /* No interrupts, no DMA, pure polling */
92 writel(0x245, &uart->ucon);
93
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090094 return 0;
95}
96
Simon Glass73e256c2014-09-14 16:36:17 -060097static int serial_err_check(const struct s5p_uart *const uart, int op)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +090098{
Minkyu Kang94003222009-11-10 20:23:50 +090099 unsigned int mask;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900100
Minkyu Kang94003222009-11-10 20:23:50 +0900101 /*
102 * UERSTAT
103 * Break Detect [3]
104 * Frame Err [2] : receive operation
105 * Parity Err [1] : receive operation
106 * Overrun Err [0] : receive operation
107 */
108 if (op)
109 mask = 0x8;
110 else
111 mask = 0xf;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900112
Minkyu Kang94003222009-11-10 20:23:50 +0900113 return readl(&uart->uerstat) & mask;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900114}
115
Simon Glass73e256c2014-09-14 16:36:17 -0600116static int s5p_serial_getc(struct udevice *dev)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900117{
Simon Glass73e256c2014-09-14 16:36:17 -0600118 struct s5p_serial_platdata *plat = dev->platdata;
119 struct s5p_uart *const uart = plat->reg;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900120
Simon Glass73e256c2014-09-14 16:36:17 -0600121 if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
122 return -EAGAIN;
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530123
Simon Glass73e256c2014-09-14 16:36:17 -0600124 serial_err_check(uart, 0);
Minkyu Kang1a4106d2010-07-06 20:08:29 +0900125 return (int)(readb(&uart->urxh) & 0xff);
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900126}
127
Simon Glass73e256c2014-09-14 16:36:17 -0600128static int s5p_serial_putc(struct udevice *dev, const char ch)
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900129{
Simon Glass73e256c2014-09-14 16:36:17 -0600130 struct s5p_serial_platdata *plat = dev->platdata;
131 struct s5p_uart *const uart = plat->reg;
Minkyu Kangdd2c9e62009-10-01 17:20:28 +0900132
Simon Glass73e256c2014-09-14 16:36:17 -0600133 if (readl(&uart->ufstat) & TX_FIFO_FULL)
134 return -EAGAIN;
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530135
Simon Glass73e256c2014-09-14 16:36:17 -0600136 writeb(ch, &uart->utxh);
137 serial_err_check(uart, 1);
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530138
139 return 0;
140}
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530141
Simon Glass73e256c2014-09-14 16:36:17 -0600142static int s5p_serial_pending(struct udevice *dev, bool input)
Mike Frysinger6c768ca2011-04-29 18:03:29 +0000143{
Simon Glass73e256c2014-09-14 16:36:17 -0600144 struct s5p_serial_platdata *plat = dev->platdata;
145 struct s5p_uart *const uart = plat->reg;
146 uint32_t ufstat = readl(&uart->ufstat);
Rajeshwari Shinded4ec8f02013-06-24 16:47:22 +0530147
Simon Glass73e256c2014-09-14 16:36:17 -0600148 if (input)
149 return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
150 else
151 return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
Mike Frysinger6c768ca2011-04-29 18:03:29 +0000152}
Marek Vasutb4980512012-09-12 19:39:57 +0200153
Simon Glass73e256c2014-09-14 16:36:17 -0600154static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
Marek Vasutb4980512012-09-12 19:39:57 +0200155{
Simon Glass73e256c2014-09-14 16:36:17 -0600156 struct s5p_serial_platdata *plat = dev->platdata;
157 fdt_addr_t addr;
158
159 addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
160 if (addr == FDT_ADDR_T_NONE)
161 return -EINVAL;
162
163 plat->reg = (struct s5p_uart *)addr;
164 plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
165
166 return 0;
Marek Vasutb4980512012-09-12 19:39:57 +0200167}
Simon Glass73e256c2014-09-14 16:36:17 -0600168
169static const struct dm_serial_ops s5p_serial_ops = {
170 .putc = s5p_serial_putc,
171 .pending = s5p_serial_pending,
172 .getc = s5p_serial_getc,
173 .setbrg = s5p_serial_setbrg,
174};
175
176static const struct udevice_id s5p_serial_ids[] = {
177 { .compatible = "samsung,exynos4210-uart" },
178 { }
179};
180
181U_BOOT_DRIVER(serial_s5p) = {
182 .name = "serial_s5p",
183 .id = UCLASS_SERIAL,
184 .of_match = s5p_serial_ids,
185 .ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
186 .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
187 .probe = s5p_serial_probe,
188 .ops = &s5p_serial_ops,
189 .flags = DM_FLAG_PRE_RELOC,
190};