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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk03f5c552004-10-10 21:21:55 +00002/*
chenhui zhao568336e2011-09-15 14:52:34 +08003 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00004 */
5
6
7#include <common.h>
8
9
10/*
11 * CADMUS Board System Registers
12 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020013#ifndef CONFIG_SYS_CADMUS_BASE_REG
14#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
wdenk03f5c552004-10-10 21:21:55 +000015#endif
16
17typedef struct cadmus_reg {
18 u_char cm_ver; /* Board version */
19 u_char cm_csr; /* General control/status */
20 u_char cm_rst; /* Reset control */
21 u_char cm_hsclk; /* High speed clock */
22 u_char cm_hsxclk; /* High speed clock extended */
23 u_char cm_led; /* LED data */
24 u_char cm_pci; /* PCI control/status */
25 u_char cm_dma; /* DMA control */
26 u_char cm_reserved[248]; /* Total 256 bytes */
27} cadmus_reg_t;
28
29
30unsigned int
31get_board_version(void)
32{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
wdenk03f5c552004-10-10 21:21:55 +000034
35 return cadmus->cm_ver;
36}
37
38
39unsigned long
40get_clock_freq(void)
41{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
wdenk03f5c552004-10-10 21:21:55 +000043
44 uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
45
46 if (pci1_speed == 0) {
chenhui zhao568336e2011-09-15 14:52:34 +080047 return 33333333;
wdenk03f5c552004-10-10 21:21:55 +000048 } else if (pci1_speed == 1) {
chenhui zhao568336e2011-09-15 14:52:34 +080049 return 66666666;
wdenk03f5c552004-10-10 21:21:55 +000050 } else {
51 /* Really, unknown. Be safe? */
chenhui zhao568336e2011-09-15 14:52:34 +080052 return 33333333;
wdenk03f5c552004-10-10 21:21:55 +000053 }
54}
55
56
57unsigned int
58get_pci_slot(void)
59{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
wdenk03f5c552004-10-10 21:21:55 +000061
62 /*
63 * PCI slot in USER bits CSR[6:7] by convention.
64 */
65 return ((cadmus->cm_csr >> 6) & 0x3) + 1;
66}
67
68
69unsigned int
70get_pci_dual(void)
71{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
wdenk03f5c552004-10-10 21:21:55 +000073
74 /*
75 * PCI DUAL in CM_PCI[3]
76 */
77 return cadmus->cm_pci & 0x10;
78}