Simon Glass | 59dd5aa | 2015-04-14 21:03:41 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2011-2013, NVIDIA Corporation. |
| 3 | * Copyright 2014 Google Inc. |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0 |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <displayport.h> |
| 10 | #include <dm.h> |
| 11 | #include <div64.h> |
| 12 | #include <errno.h> |
| 13 | #include <fdtdec.h> |
| 14 | #include <asm/io.h> |
| 15 | #include <asm/arch-tegra/dc.h> |
| 16 | #include "displayport.h" |
| 17 | #include "edid.h" |
| 18 | #include "sor.h" |
| 19 | |
| 20 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | |
| 22 | struct tegra_dp_plat { |
| 23 | ulong base; |
| 24 | }; |
| 25 | |
| 26 | struct tegra_dp_priv { |
| 27 | struct dpaux_ctlr *regs; |
| 28 | struct tegra_dc_sor_data *sor; |
| 29 | u8 revision; |
| 30 | int enabled; |
| 31 | }; |
| 32 | |
| 33 | struct tegra_dp_priv dp_data; |
| 34 | |
| 35 | static inline u32 tegra_dpaux_readl(struct tegra_dp_priv *dp, u32 reg) |
| 36 | { |
| 37 | return readl((u32 *)dp->regs + reg); |
| 38 | } |
| 39 | |
| 40 | static inline void tegra_dpaux_writel(struct tegra_dp_priv *dp, u32 reg, |
| 41 | u32 val) |
| 42 | { |
| 43 | writel(val, (u32 *)dp->regs + reg); |
| 44 | } |
| 45 | |
| 46 | static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dp_priv *dp, |
| 47 | u32 reg, u32 mask, u32 exp_val, |
| 48 | u32 poll_interval_us, |
| 49 | u32 timeout_us) |
| 50 | { |
| 51 | u32 reg_val = 0; |
| 52 | u32 temp = timeout_us; |
| 53 | |
| 54 | do { |
| 55 | udelay(poll_interval_us); |
| 56 | reg_val = tegra_dpaux_readl(dp, reg); |
| 57 | if (timeout_us > poll_interval_us) |
| 58 | timeout_us -= poll_interval_us; |
| 59 | else |
| 60 | break; |
| 61 | } while ((reg_val & mask) != exp_val); |
| 62 | |
| 63 | if ((reg_val & mask) == exp_val) |
| 64 | return 0; /* success */ |
| 65 | debug("dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", |
| 66 | reg, reg_val, mask, exp_val); |
| 67 | return temp; |
| 68 | } |
| 69 | |
| 70 | static inline int tegra_dpaux_wait_transaction(struct tegra_dp_priv *dp) |
| 71 | { |
| 72 | /* According to DP spec, each aux transaction needs to finish |
| 73 | within 40ms. */ |
| 74 | if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, |
| 75 | DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, |
| 76 | DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, |
| 77 | 100, DP_AUX_TIMEOUT_MS * 1000) != 0) { |
| 78 | debug("dp: DPAUX transaction timeout\n"); |
| 79 | return -1; |
| 80 | } |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static int tegra_dc_dpaux_write_chunk(struct tegra_dp_priv *dp, u32 cmd, |
| 85 | u32 addr, u8 *data, u32 *size, |
| 86 | u32 *aux_stat) |
| 87 | { |
| 88 | int i; |
| 89 | u32 reg_val; |
| 90 | u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; |
| 91 | u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; |
| 92 | u32 temp_data; |
| 93 | |
| 94 | if (*size > DP_AUX_MAX_BYTES) |
| 95 | return -1; /* only write one chunk of data */ |
| 96 | |
| 97 | /* Make sure the command is write command */ |
| 98 | switch (cmd) { |
| 99 | case DPAUX_DP_AUXCTL_CMD_I2CWR: |
| 100 | case DPAUX_DP_AUXCTL_CMD_MOTWR: |
| 101 | case DPAUX_DP_AUXCTL_CMD_AUXWR: |
| 102 | break; |
| 103 | default: |
| 104 | debug("dp: aux write cmd 0x%x is invalid\n", cmd); |
| 105 | return -EINVAL; |
| 106 | } |
| 107 | |
| 108 | tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); |
| 109 | for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) { |
| 110 | memcpy(&temp_data, data, 4); |
| 111 | tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data); |
| 112 | data += 4; |
| 113 | } |
| 114 | |
| 115 | reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); |
| 116 | reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; |
| 117 | reg_val |= cmd; |
| 118 | reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; |
| 119 | reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); |
| 120 | |
| 121 | while ((timeout_retries > 0) && (defer_retries > 0)) { |
| 122 | if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || |
| 123 | (defer_retries != DP_AUX_DEFER_MAX_TRIES)) |
| 124 | udelay(1); |
| 125 | |
| 126 | reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; |
| 127 | tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); |
| 128 | |
| 129 | if (tegra_dpaux_wait_transaction(dp)) |
| 130 | debug("dp: aux write transaction timeout\n"); |
| 131 | |
| 132 | *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); |
| 133 | |
| 134 | if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || |
| 135 | (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || |
| 136 | (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || |
| 137 | (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { |
| 138 | if (timeout_retries-- > 0) { |
| 139 | debug("dp: aux write retry (0x%x) -- %d\n", |
| 140 | *aux_stat, timeout_retries); |
| 141 | /* clear the error bits */ |
| 142 | tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, |
| 143 | *aux_stat); |
| 144 | continue; |
| 145 | } else { |
| 146 | debug("dp: aux write got error (0x%x)\n", |
| 147 | *aux_stat); |
| 148 | return -ETIMEDOUT; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || |
| 153 | (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { |
| 154 | if (defer_retries-- > 0) { |
| 155 | debug("dp: aux write defer (0x%x) -- %d\n", |
| 156 | *aux_stat, defer_retries); |
| 157 | /* clear the error bits */ |
| 158 | tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, |
| 159 | *aux_stat); |
| 160 | continue; |
| 161 | } else { |
| 162 | debug("dp: aux write defer exceeds max retries (0x%x)\n", |
| 163 | *aux_stat); |
| 164 | return -ETIMEDOUT; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == |
| 169 | DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { |
| 170 | *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); |
| 171 | return 0; |
| 172 | } else { |
| 173 | debug("dp: aux write failed (0x%x)\n", *aux_stat); |
| 174 | return -EIO; |
| 175 | } |
| 176 | } |
| 177 | /* Should never come to here */ |
| 178 | return -EIO; |
| 179 | } |
| 180 | |
| 181 | static int tegra_dc_dpaux_read_chunk(struct tegra_dp_priv *dp, u32 cmd, |
| 182 | u32 addr, u8 *data, u32 *size, |
| 183 | u32 *aux_stat) |
| 184 | { |
| 185 | u32 reg_val; |
| 186 | u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; |
| 187 | u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; |
| 188 | |
| 189 | if (*size > DP_AUX_MAX_BYTES) { |
| 190 | debug("only read one chunk\n"); |
| 191 | return -EIO; /* only read one chunk */ |
| 192 | } |
| 193 | |
| 194 | /* Check to make sure the command is read command */ |
| 195 | switch (cmd) { |
| 196 | case DPAUX_DP_AUXCTL_CMD_I2CRD: |
| 197 | case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT: |
| 198 | case DPAUX_DP_AUXCTL_CMD_MOTRD: |
| 199 | case DPAUX_DP_AUXCTL_CMD_AUXRD: |
| 200 | break; |
| 201 | default: |
| 202 | debug("dp: aux read cmd 0x%x is invalid\n", cmd); |
| 203 | return -EIO; |
| 204 | } |
| 205 | |
| 206 | *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); |
| 207 | if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { |
| 208 | debug("dp: HPD is not detected\n"); |
| 209 | return -EIO; |
| 210 | } |
| 211 | |
| 212 | tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); |
| 213 | |
| 214 | reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); |
| 215 | reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; |
| 216 | reg_val |= cmd; |
| 217 | reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; |
| 218 | reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); |
| 219 | while ((timeout_retries > 0) && (defer_retries > 0)) { |
| 220 | if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || |
| 221 | (defer_retries != DP_AUX_DEFER_MAX_TRIES)) |
| 222 | udelay(DP_DPCP_RETRY_SLEEP_NS * 2); |
| 223 | |
| 224 | reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; |
| 225 | tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); |
| 226 | |
| 227 | if (tegra_dpaux_wait_transaction(dp)) |
| 228 | debug("dp: aux read transaction timeout\n"); |
| 229 | |
| 230 | *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); |
| 231 | |
| 232 | if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || |
| 233 | (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || |
| 234 | (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || |
| 235 | (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { |
| 236 | if (timeout_retries-- > 0) { |
| 237 | debug("dp: aux read retry (0x%x) -- %d\n", |
| 238 | *aux_stat, timeout_retries); |
| 239 | /* clear the error bits */ |
| 240 | tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, |
| 241 | *aux_stat); |
| 242 | continue; /* retry */ |
| 243 | } else { |
| 244 | debug("dp: aux read got error (0x%x)\n", |
| 245 | *aux_stat); |
| 246 | return -ETIMEDOUT; |
| 247 | } |
| 248 | } |
| 249 | |
| 250 | if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || |
| 251 | (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { |
| 252 | if (defer_retries-- > 0) { |
| 253 | debug("dp: aux read defer (0x%x) -- %d\n", |
| 254 | *aux_stat, defer_retries); |
| 255 | /* clear the error bits */ |
| 256 | tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, |
| 257 | *aux_stat); |
| 258 | continue; |
| 259 | } else { |
| 260 | debug("dp: aux read defer exceeds max retries (0x%x)\n", |
| 261 | *aux_stat); |
| 262 | return -ETIMEDOUT; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == |
| 267 | DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { |
| 268 | int i; |
| 269 | u32 temp_data[4]; |
| 270 | |
| 271 | for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) |
| 272 | temp_data[i] = tegra_dpaux_readl(dp, |
| 273 | DPAUX_DP_AUXDATA_READ_W(i)); |
| 274 | |
| 275 | *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); |
| 276 | memcpy(data, temp_data, *size); |
| 277 | |
| 278 | return 0; |
| 279 | } else { |
| 280 | debug("dp: aux read failed (0x%x\n", *aux_stat); |
| 281 | return -EIO; |
| 282 | } |
| 283 | } |
| 284 | /* Should never come to here */ |
| 285 | debug("%s: can't\n", __func__); |
| 286 | |
| 287 | return -EIO; |
| 288 | } |
| 289 | |
| 290 | static int tegra_dc_dpaux_read(struct tegra_dp_priv *dp, u32 cmd, u32 addr, |
| 291 | u8 *data, u32 *size, u32 *aux_stat) |
| 292 | { |
| 293 | u32 finished = 0; |
| 294 | u32 cur_size; |
| 295 | int ret = 0; |
| 296 | |
| 297 | do { |
| 298 | cur_size = *size - finished; |
| 299 | if (cur_size > DP_AUX_MAX_BYTES) |
| 300 | cur_size = DP_AUX_MAX_BYTES; |
| 301 | |
| 302 | ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, |
| 303 | data, &cur_size, aux_stat); |
| 304 | if (ret) |
| 305 | break; |
| 306 | |
| 307 | /* cur_size should be the real size returned */ |
| 308 | addr += cur_size; |
| 309 | data += cur_size; |
| 310 | finished += cur_size; |
| 311 | |
| 312 | } while (*size > finished); |
| 313 | *size = finished; |
| 314 | |
| 315 | return ret; |
| 316 | } |
| 317 | |
| 318 | static int tegra_dc_dp_dpcd_read(struct tegra_dp_priv *dp, u32 cmd, |
| 319 | u8 *data_ptr) |
| 320 | { |
| 321 | u32 size = 1; |
| 322 | u32 status = 0; |
| 323 | int ret; |
| 324 | |
| 325 | ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, |
| 326 | cmd, data_ptr, &size, &status); |
| 327 | if (ret) { |
| 328 | debug("dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", |
| 329 | cmd, status); |
| 330 | } |
| 331 | |
| 332 | return ret; |
| 333 | } |
| 334 | |
| 335 | static int tegra_dc_dp_dpcd_write(struct tegra_dp_priv *dp, u32 cmd, |
| 336 | u8 data) |
| 337 | { |
| 338 | u32 size = 1; |
| 339 | u32 status = 0; |
| 340 | int ret; |
| 341 | |
| 342 | ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, |
| 343 | cmd, &data, &size, &status); |
| 344 | if (ret) { |
| 345 | debug("dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n", |
| 346 | cmd, status); |
| 347 | } |
| 348 | |
| 349 | return ret; |
| 350 | } |
| 351 | |
| 352 | static int tegra_dc_i2c_aux_read(struct tegra_dp_priv *dp, u32 i2c_addr, |
| 353 | u8 addr, u8 *data, u32 size, u32 *aux_stat) |
| 354 | { |
| 355 | u32 finished = 0; |
| 356 | int ret = 0; |
| 357 | |
| 358 | do { |
| 359 | u32 cur_size = min((u32)DP_AUX_MAX_BYTES, size - finished); |
| 360 | |
| 361 | u32 len = 1; |
| 362 | ret = tegra_dc_dpaux_write_chunk( |
| 363 | dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr, |
| 364 | &addr, &len, aux_stat); |
| 365 | if (ret) { |
| 366 | debug("%s: error sending address to read.\n", |
| 367 | __func__); |
| 368 | return ret; |
| 369 | } |
| 370 | |
| 371 | ret = tegra_dc_dpaux_read_chunk( |
| 372 | dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr, |
| 373 | data, &cur_size, aux_stat); |
| 374 | if (ret) { |
| 375 | debug("%s: error reading data.\n", __func__); |
| 376 | return ret; |
| 377 | } |
| 378 | |
| 379 | /* cur_size should be the real size returned */ |
| 380 | addr += cur_size; |
| 381 | data += cur_size; |
| 382 | finished += cur_size; |
| 383 | } while (size > finished); |
| 384 | |
| 385 | return finished; |
| 386 | } |
| 387 | |
| 388 | static void tegra_dc_dpaux_enable(struct tegra_dp_priv *dp) |
| 389 | { |
| 390 | /* clear interrupt */ |
| 391 | tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff); |
| 392 | /* do not enable interrupt for now. Enable them when Isr in place */ |
| 393 | tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0); |
| 394 | |
| 395 | tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, |
| 396 | DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 | |
| 397 | DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 | |
| 398 | 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT | |
| 399 | DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE); |
| 400 | |
| 401 | tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, |
| 402 | DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP); |
| 403 | } |
| 404 | |
| 405 | #ifdef DEBUG |
| 406 | static void tegra_dc_dp_dump_link_cfg(struct tegra_dp_priv *dp, |
| 407 | const struct tegra_dp_link_config *link_cfg) |
| 408 | { |
| 409 | debug("DP config: cfg_name cfg_value\n"); |
| 410 | debug(" Lane Count %d\n", |
| 411 | link_cfg->max_lane_count); |
| 412 | debug(" SupportEnhancedFraming %s\n", |
| 413 | link_cfg->support_enhanced_framing ? "Y" : "N"); |
| 414 | debug(" Bandwidth %d\n", |
| 415 | link_cfg->max_link_bw); |
| 416 | debug(" bpp %d\n", |
| 417 | link_cfg->bits_per_pixel); |
| 418 | debug(" EnhancedFraming %s\n", |
| 419 | link_cfg->enhanced_framing ? "Y" : "N"); |
| 420 | debug(" Scramble_enabled %s\n", |
| 421 | link_cfg->scramble_ena ? "Y" : "N"); |
| 422 | debug(" LinkBW %d\n", |
| 423 | link_cfg->link_bw); |
| 424 | debug(" lane_count %d\n", |
| 425 | link_cfg->lane_count); |
| 426 | debug(" activespolarity %d\n", |
| 427 | link_cfg->activepolarity); |
| 428 | debug(" active_count %d\n", |
| 429 | link_cfg->active_count); |
| 430 | debug(" tu_size %d\n", |
| 431 | link_cfg->tu_size); |
| 432 | debug(" active_frac %d\n", |
| 433 | link_cfg->active_frac); |
| 434 | debug(" watermark %d\n", |
| 435 | link_cfg->watermark); |
| 436 | debug(" hblank_sym %d\n", |
| 437 | link_cfg->hblank_sym); |
| 438 | debug(" vblank_sym %d\n", |
| 439 | link_cfg->vblank_sym); |
| 440 | } |
| 441 | #endif |
| 442 | |
| 443 | /* |
| 444 | * Calcuate if given cfg can meet the mode request. |
| 445 | * Return 0 if mode is possible, -1 otherwise |
| 446 | */ |
| 447 | static int tegra_dc_dp_calc_config(struct tegra_dp_priv *dp, |
| 448 | const struct display_timing *timing, |
| 449 | struct tegra_dp_link_config *link_cfg) |
| 450 | { |
| 451 | const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000; |
| 452 | const u64 f = 100000; /* precision factor */ |
| 453 | u32 num_linkclk_line; /* Number of link clocks per line */ |
| 454 | u64 ratio_f; /* Ratio of incoming to outgoing data rate */ |
| 455 | u64 frac_f; |
| 456 | u64 activesym_f; /* Activesym per TU */ |
| 457 | u64 activecount_f; |
| 458 | u32 activecount; |
| 459 | u32 activepolarity; |
| 460 | u64 approx_value_f; |
| 461 | u32 activefrac = 0; |
| 462 | u64 accumulated_error_f = 0; |
| 463 | u32 lowest_neg_activecount = 0; |
| 464 | u32 lowest_neg_activepolarity = 0; |
| 465 | u32 lowest_neg_tusize = 64; |
| 466 | u32 num_symbols_per_line; |
| 467 | u64 lowest_neg_activefrac = 0; |
| 468 | u64 lowest_neg_error_f = 64 * f; |
| 469 | u64 watermark_f; |
| 470 | int i; |
| 471 | int neg; |
| 472 | |
| 473 | if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || |
| 474 | !link_cfg->bits_per_pixel) |
| 475 | return -1; |
| 476 | |
| 477 | if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= |
| 478 | (u64)link_rate * 8 * link_cfg->lane_count) |
| 479 | return -1; |
| 480 | |
| 481 | num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ, |
| 482 | timing->pixelclock.typ)); |
| 483 | |
| 484 | ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; |
| 485 | ratio_f /= 8; |
| 486 | do_div(ratio_f, link_rate * link_cfg->lane_count); |
| 487 | |
| 488 | for (i = 64; i >= 32; --i) { |
| 489 | activesym_f = ratio_f * i; |
| 490 | activecount_f = lldiv(activesym_f, (u32)f) * f; |
| 491 | frac_f = activesym_f - activecount_f; |
| 492 | activecount = (u32)(lldiv(activecount_f, (u32)f)); |
| 493 | |
| 494 | if (frac_f < (lldiv(f, 2))) /* fraction < 0.5 */ |
| 495 | activepolarity = 0; |
| 496 | else { |
| 497 | activepolarity = 1; |
| 498 | frac_f = f - frac_f; |
| 499 | } |
| 500 | |
| 501 | if (frac_f != 0) { |
| 502 | /* warning: frac_f should be 64-bit */ |
| 503 | frac_f = lldiv(f * f, frac_f); /* 1 / fraction */ |
| 504 | if (frac_f > (15 * f)) |
| 505 | activefrac = activepolarity ? 1 : 15; |
| 506 | else |
| 507 | activefrac = activepolarity ? |
| 508 | (u32)lldiv(frac_f, (u32)f) + 1 : |
| 509 | (u32)lldiv(frac_f, (u32)f); |
| 510 | } |
| 511 | |
| 512 | if (activefrac == 1) |
| 513 | activepolarity = 0; |
| 514 | |
| 515 | if (activepolarity == 1) |
| 516 | approx_value_f = activefrac ? lldiv( |
| 517 | (activecount_f + (activefrac * f - f) * f), |
| 518 | (activefrac * f)) : |
| 519 | activecount_f + f; |
| 520 | else |
| 521 | approx_value_f = activefrac ? |
| 522 | activecount_f + lldiv(f, activefrac) : |
| 523 | activecount_f; |
| 524 | |
| 525 | if (activesym_f < approx_value_f) { |
| 526 | accumulated_error_f = num_linkclk_line * |
| 527 | lldiv(approx_value_f - activesym_f, i); |
| 528 | neg = 1; |
| 529 | } else { |
| 530 | accumulated_error_f = num_linkclk_line * |
| 531 | lldiv(activesym_f - approx_value_f, i); |
| 532 | neg = 0; |
| 533 | } |
| 534 | |
| 535 | if ((neg && (lowest_neg_error_f > accumulated_error_f)) || |
| 536 | (accumulated_error_f == 0)) { |
| 537 | lowest_neg_error_f = accumulated_error_f; |
| 538 | lowest_neg_tusize = i; |
| 539 | lowest_neg_activecount = activecount; |
| 540 | lowest_neg_activepolarity = activepolarity; |
| 541 | lowest_neg_activefrac = activefrac; |
| 542 | |
| 543 | if (accumulated_error_f == 0) |
| 544 | break; |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | if (lowest_neg_activefrac == 0) { |
| 549 | link_cfg->activepolarity = 0; |
| 550 | link_cfg->active_count = lowest_neg_activepolarity ? |
| 551 | lowest_neg_activecount : lowest_neg_activecount - 1; |
| 552 | link_cfg->tu_size = lowest_neg_tusize; |
| 553 | link_cfg->active_frac = 1; |
| 554 | } else { |
| 555 | link_cfg->activepolarity = lowest_neg_activepolarity; |
| 556 | link_cfg->active_count = (u32)lowest_neg_activecount; |
| 557 | link_cfg->tu_size = lowest_neg_tusize; |
| 558 | link_cfg->active_frac = (u32)lowest_neg_activefrac; |
| 559 | } |
| 560 | |
| 561 | watermark_f = lldiv(ratio_f * link_cfg->tu_size * (f - ratio_f), f); |
| 562 | link_cfg->watermark = (u32)(lldiv(watermark_f + lowest_neg_error_f, |
| 563 | f)) + link_cfg->bits_per_pixel / 4 - 1; |
| 564 | num_symbols_per_line = (timing->hactive.typ * |
| 565 | link_cfg->bits_per_pixel) / |
| 566 | (8 * link_cfg->lane_count); |
| 567 | |
| 568 | if (link_cfg->watermark > 30) { |
| 569 | debug("dp: sor setting: unable to get a good tusize, force watermark to 30\n"); |
| 570 | link_cfg->watermark = 30; |
| 571 | return -1; |
| 572 | } else if (link_cfg->watermark > num_symbols_per_line) { |
| 573 | debug("dp: sor setting: force watermark to the number of symbols in the line\n"); |
| 574 | link_cfg->watermark = num_symbols_per_line; |
| 575 | return -1; |
| 576 | } |
| 577 | |
| 578 | /* |
| 579 | * Refer to dev_disp.ref for more information. |
| 580 | * # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - |
| 581 | * SetRasterBlankStart.X - 7) * link_clk / pclk) |
| 582 | * - 3 * enhanced_framing - Y |
| 583 | * where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 |
| 584 | */ |
| 585 | link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ + |
| 586 | timing->hfront_porch.typ + timing->hsync_len.typ - 7) * |
| 587 | link_rate, timing->pixelclock.typ) - |
| 588 | 3 * link_cfg->enhanced_framing - |
| 589 | (12 / link_cfg->lane_count); |
| 590 | |
| 591 | if (link_cfg->hblank_sym < 0) |
| 592 | link_cfg->hblank_sym = 0; |
| 593 | |
| 594 | |
| 595 | /* |
| 596 | * Refer to dev_disp.ref for more information. |
| 597 | * # symbols/vblank = ((SetRasterBlankStart.X - |
| 598 | * SetRasterBlankEen.X - 25) * link_clk / pclk) |
| 599 | * - Y - 1; |
| 600 | * where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 |
| 601 | */ |
| 602 | link_cfg->vblank_sym = (int)lldiv(((uint64_t)timing->hactive.typ - 25) |
| 603 | * link_rate, timing->pixelclock.typ) - (36 / |
| 604 | link_cfg->lane_count) - 4; |
| 605 | |
| 606 | if (link_cfg->vblank_sym < 0) |
| 607 | link_cfg->vblank_sym = 0; |
| 608 | |
| 609 | link_cfg->is_valid = 1; |
| 610 | #ifdef DEBUG |
| 611 | tegra_dc_dp_dump_link_cfg(dp, link_cfg); |
| 612 | #endif |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | static int tegra_dc_dp_init_max_link_cfg( |
| 618 | const struct display_timing *timing, |
| 619 | struct tegra_dp_priv *dp, |
| 620 | struct tegra_dp_link_config *link_cfg) |
| 621 | { |
| 622 | const int drive_current = 0x40404040; |
| 623 | const int preemphasis = 0x0f0f0f0f; |
| 624 | const int postcursor = 0; |
| 625 | u8 dpcd_data; |
| 626 | int ret; |
| 627 | |
| 628 | ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data); |
| 629 | if (ret) |
| 630 | return ret; |
| 631 | link_cfg->max_lane_count = dpcd_data & DP_MAX_LANE_COUNT_MASK; |
| 632 | |
| 633 | link_cfg->support_enhanced_framing = |
| 634 | (dpcd_data & DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? |
| 635 | 1 : 0; |
| 636 | |
| 637 | ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data); |
| 638 | if (ret) |
| 639 | return ret; |
| 640 | link_cfg->downspread = (dpcd_data & DP_MAX_DOWNSPREAD_VAL_0_5_PCT) ? |
| 641 | 1 : 0; |
| 642 | |
| 643 | ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE, |
| 644 | &link_cfg->max_link_bw); |
| 645 | if (ret) |
| 646 | return ret; |
| 647 | |
| 648 | /* |
| 649 | * Set to a high value for link training and attach. |
| 650 | * Will be re-programmed when dp is enabled. |
| 651 | */ |
| 652 | link_cfg->drive_current = drive_current; |
| 653 | link_cfg->preemphasis = preemphasis; |
| 654 | link_cfg->postcursor = postcursor; |
| 655 | |
| 656 | ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data); |
| 657 | if (ret) |
| 658 | return ret; |
| 659 | |
| 660 | link_cfg->alt_scramber_reset_cap = |
| 661 | (dpcd_data & DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES) ? |
| 662 | 1 : 0; |
| 663 | link_cfg->only_enhanced_framing = |
| 664 | (dpcd_data & DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES) ? |
| 665 | 1 : 0; |
| 666 | |
| 667 | link_cfg->lane_count = link_cfg->max_lane_count; |
| 668 | link_cfg->link_bw = link_cfg->max_link_bw; |
| 669 | link_cfg->enhanced_framing = link_cfg->support_enhanced_framing; |
| 670 | |
| 671 | tegra_dc_dp_calc_config(dp, timing, link_cfg); |
| 672 | return 0; |
| 673 | } |
| 674 | |
| 675 | static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp, |
| 676 | struct tegra_dc_sor_data *sor, int ena) |
| 677 | { |
| 678 | int ret; |
| 679 | |
| 680 | u8 dpcd_data = ena ? |
| 681 | DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE : |
| 682 | DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE; |
| 683 | |
| 684 | ret = tegra_dc_dp_dpcd_write(dp, DP_EDP_CONFIGURATION_SET, |
| 685 | dpcd_data); |
| 686 | if (ret) |
| 687 | return ret; |
| 688 | |
| 689 | /* Also reset the scrambler to 0xfffe */ |
| 690 | tegra_dc_sor_set_internal_panel(sor, ena); |
| 691 | return 0; |
| 692 | } |
| 693 | |
| 694 | static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp, |
| 695 | struct tegra_dc_sor_data *sor, |
| 696 | u8 link_bw) |
| 697 | { |
| 698 | tegra_dc_sor_set_link_bandwidth(sor, link_bw); |
| 699 | |
| 700 | /* Sink side */ |
| 701 | return tegra_dc_dp_dpcd_write(dp, DP_LINK_BW_SET, link_bw); |
| 702 | } |
| 703 | |
| 704 | static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp, |
| 705 | const struct tegra_dp_link_config *link_cfg, |
| 706 | struct tegra_dc_sor_data *sor) |
| 707 | { |
| 708 | u8 dpcd_data; |
| 709 | int ret; |
| 710 | |
| 711 | /* check if panel support enhanched_framing */ |
| 712 | dpcd_data = link_cfg->lane_count; |
| 713 | if (link_cfg->enhanced_framing) |
| 714 | dpcd_data |= DP_LANE_COUNT_SET_ENHANCEDFRAMING_T; |
| 715 | ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data); |
| 716 | if (ret) |
| 717 | return ret; |
| 718 | |
| 719 | tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); |
| 720 | |
| 721 | /* Also power down lanes that will not be used */ |
| 722 | return 0; |
| 723 | } |
| 724 | |
| 725 | static int tegra_dc_dp_link_trained(struct tegra_dp_priv *dp, |
| 726 | const struct tegra_dp_link_config *cfg) |
| 727 | { |
| 728 | u32 lane; |
| 729 | u8 mask; |
| 730 | u8 data; |
| 731 | int ret; |
| 732 | |
| 733 | for (lane = 0; lane < cfg->lane_count; ++lane) { |
| 734 | ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ? |
| 735 | DP_LANE2_3_STATUS : DP_LANE0_1_STATUS, |
| 736 | &data); |
| 737 | if (ret) |
| 738 | return ret; |
| 739 | mask = (lane & 1) ? |
| 740 | NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES | |
| 741 | NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES | |
| 742 | NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES : |
| 743 | DP_LANE_CR_DONE | |
| 744 | DP_LANE_CHANNEL_EQ_DONE | |
| 745 | DP_LANE_SYMBOL_LOCKED; |
| 746 | if ((data & mask) != mask) |
| 747 | return -1; |
| 748 | } |
| 749 | return 0; |
| 750 | } |
| 751 | |
| 752 | /* |
| 753 | * All link training functions are ported from kernel dc driver. |
| 754 | * See more details at drivers/video/tegra/dc/dp.c |
| 755 | */ |
| 756 | static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp, |
| 757 | const struct tegra_dp_link_config *link_cfg, |
| 758 | struct tegra_dc_sor_data *sor) |
| 759 | { |
| 760 | u8 link_bw; |
| 761 | u8 lane_count; |
| 762 | u16 data16; |
| 763 | u32 data32; |
| 764 | u32 size; |
| 765 | u32 status; |
| 766 | int j; |
| 767 | u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4); |
| 768 | |
| 769 | tegra_dc_sor_set_lane_parm(sor, link_cfg); |
| 770 | tegra_dc_dp_dpcd_write(dp, DP_MAIN_LINK_CHANNEL_CODING_SET, |
| 771 | DP_SET_ANSI_8B10B); |
| 772 | |
| 773 | /* Send TP1 */ |
| 774 | tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg); |
| 775 | tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, |
| 776 | DP_TRAINING_PATTERN_1); |
| 777 | |
| 778 | for (j = 0; j < link_cfg->lane_count; ++j) |
| 779 | tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); |
| 780 | udelay(520); |
| 781 | |
| 782 | size = sizeof(data16); |
| 783 | tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, |
| 784 | DP_LANE0_1_STATUS, (u8 *)&data16, &size, &status); |
| 785 | status = mask & 0x1111; |
| 786 | if ((data16 & status) != status) { |
| 787 | debug("dp: Link training error for TP1 (%#x, status %#x)\n", |
| 788 | data16, status); |
| 789 | return -EFAULT; |
| 790 | } |
| 791 | |
| 792 | /* enable ASSR */ |
| 793 | tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena); |
| 794 | tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg); |
| 795 | |
| 796 | tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, |
| 797 | link_cfg->link_bw == 20 ? 0x23 : 0x22); |
| 798 | for (j = 0; j < link_cfg->lane_count; ++j) |
| 799 | tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); |
| 800 | udelay(520); |
| 801 | |
| 802 | size = sizeof(data32); |
| 803 | tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, DP_LANE0_1_STATUS, |
| 804 | (u8 *)&data32, &size, &status); |
| 805 | if ((data32 & mask) != (0x7777 & mask)) { |
| 806 | debug("dp: Link training error for TP2/3 (0x%x)\n", data32); |
| 807 | return -EFAULT; |
| 808 | } |
| 809 | |
| 810 | tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled, |
| 811 | link_cfg); |
| 812 | tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, 0); |
| 813 | |
| 814 | if (tegra_dc_dp_link_trained(dp, link_cfg)) { |
| 815 | tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count); |
| 816 | debug("Fast link training failed, link bw %d, lane # %d\n", |
| 817 | link_bw, lane_count); |
| 818 | return -EFAULT; |
| 819 | } |
| 820 | |
| 821 | debug("Fast link training succeeded, link bw %d, lane %d\n", |
| 822 | link_cfg->link_bw, link_cfg->lane_count); |
| 823 | |
| 824 | return 0; |
| 825 | } |
| 826 | |
| 827 | static int tegra_dp_link_config(struct tegra_dp_priv *dp, |
| 828 | const struct tegra_dp_link_config *link_cfg, |
| 829 | struct tegra_dc_sor_data *sor) |
| 830 | { |
| 831 | u8 dpcd_data; |
| 832 | u8 link_bw; |
| 833 | u8 lane_count; |
| 834 | u32 retry; |
| 835 | int ret; |
| 836 | |
| 837 | if (link_cfg->lane_count == 0) { |
| 838 | debug("dp: error: lane count is 0. Can not set link config.\n"); |
| 839 | return -1; |
| 840 | } |
| 841 | |
| 842 | /* Set power state if it is not in normal level */ |
| 843 | ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data); |
| 844 | if (ret) |
| 845 | return ret; |
| 846 | if (dpcd_data == DP_SET_POWER_D3) { |
| 847 | dpcd_data = DP_SET_POWER_D0; |
| 848 | retry = 3; /* DP spec requires 3 retries */ |
| 849 | do { |
| 850 | ret = tegra_dc_dp_dpcd_write(dp, |
| 851 | DP_SET_POWER, dpcd_data); |
| 852 | } while ((--retry > 0) && ret); |
| 853 | if (ret) { |
| 854 | debug("dp: Failed to set DP panel power\n"); |
| 855 | return ret; |
| 856 | } |
| 857 | } |
| 858 | |
| 859 | /* Enable ASSR if possible */ |
| 860 | if (link_cfg->alt_scramber_reset_cap) { |
| 861 | ret = tegra_dc_dp_set_assr(dp, sor, 1); |
| 862 | if (ret) |
| 863 | return ret; |
| 864 | } |
| 865 | |
| 866 | ret = tegra_dp_set_link_bandwidth(dp, sor, link_cfg->link_bw); |
| 867 | if (ret) { |
| 868 | debug("dp: Failed to set link bandwidth\n"); |
| 869 | return ret; |
| 870 | } |
| 871 | ret = tegra_dp_set_lane_count(dp, link_cfg, sor); |
| 872 | if (ret) { |
| 873 | debug("dp: Failed to set lane count\n"); |
| 874 | return ret; |
| 875 | } |
| 876 | tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg); |
| 877 | |
| 878 | /* Now do the fast link training for eDP */ |
| 879 | ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor); |
| 880 | if (ret) { |
| 881 | debug("dp: fast link training failed\n"); |
| 882 | return ret; |
| 883 | } |
| 884 | |
| 885 | /* Everything is good; double check the link config */ |
| 886 | tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count); |
| 887 | |
| 888 | if ((link_cfg->link_bw == link_bw) && |
| 889 | (link_cfg->lane_count == lane_count)) |
| 890 | return 0; |
| 891 | else |
| 892 | return -EFAULT; |
| 893 | } |
| 894 | |
| 895 | static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp, |
| 896 | struct tegra_dp_link_config *link_cfg, |
| 897 | struct tegra_dc_sor_data *sor, |
| 898 | const struct display_timing *timing) |
| 899 | { |
| 900 | struct tegra_dp_link_config temp_cfg; |
| 901 | |
| 902 | if (!timing->pixelclock.typ || !timing->hactive.typ || |
| 903 | !timing->vactive.typ) { |
| 904 | debug("dp: error mode configuration"); |
| 905 | return -EINVAL; |
| 906 | } |
| 907 | if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) { |
| 908 | debug("dp: error link configuration"); |
| 909 | return -EINVAL; |
| 910 | } |
| 911 | |
| 912 | link_cfg->is_valid = 0; |
| 913 | |
| 914 | memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg)); |
| 915 | |
| 916 | temp_cfg.link_bw = temp_cfg.max_link_bw; |
| 917 | temp_cfg.lane_count = temp_cfg.max_lane_count; |
| 918 | |
| 919 | /* |
| 920 | * set to max link config |
| 921 | */ |
| 922 | if ((!tegra_dc_dp_calc_config(dp, timing, &temp_cfg)) && |
| 923 | (!(tegra_dp_link_config(dp, &temp_cfg, sor)))) |
| 924 | /* the max link cfg is doable */ |
| 925 | memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg)); |
| 926 | |
| 927 | return link_cfg->is_valid ? 0 : -EFAULT; |
| 928 | } |
| 929 | |
| 930 | static int tegra_dp_hpd_plug(struct tegra_dp_priv *dp) |
| 931 | { |
| 932 | const int vdd_to_hpd_delay_ms = 200; |
| 933 | u32 val; |
| 934 | ulong start; |
| 935 | |
| 936 | start = get_timer(0); |
| 937 | do { |
| 938 | val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); |
| 939 | if (val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED) |
| 940 | return 0; |
| 941 | udelay(100); |
| 942 | } while (get_timer(start) < vdd_to_hpd_delay_ms); |
| 943 | |
| 944 | return -EIO; |
| 945 | } |
| 946 | |
| 947 | int tegra_dp_enable(struct udevice *dev, int panel_bpp, |
| 948 | const struct display_timing *timing) |
| 949 | { |
| 950 | struct tegra_dp_priv *priv = dev_get_priv(dev); |
| 951 | struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg; |
| 952 | struct tegra_dc_sor_data *sor; |
| 953 | int data; |
| 954 | int retry; |
| 955 | int ret; |
| 956 | |
| 957 | memset(link_cfg, '\0', sizeof(*link_cfg)); |
| 958 | link_cfg->is_valid = 0; |
| 959 | link_cfg->scramble_ena = 1; |
| 960 | |
| 961 | tegra_dc_dpaux_enable(priv); |
| 962 | |
| 963 | if (tegra_dp_hpd_plug(priv) < 0) { |
| 964 | debug("dp: hpd plug failed\n"); |
| 965 | return -EIO; |
| 966 | } |
| 967 | |
| 968 | link_cfg->bits_per_pixel = panel_bpp; |
| 969 | if (tegra_dc_dp_init_max_link_cfg(timing, priv, link_cfg)) { |
| 970 | debug("dp: failed to init link configuration\n"); |
| 971 | return -ENOLINK; |
| 972 | } |
| 973 | |
| 974 | ret = tegra_dc_sor_init(&sor); |
| 975 | if (ret) |
| 976 | return ret; |
| 977 | priv->sor = sor; |
| 978 | ret = tegra_dc_sor_enable_dp(sor, link_cfg); |
| 979 | if (ret) |
| 980 | return ret; |
| 981 | |
| 982 | tegra_dc_sor_set_panel_power(sor, 1); |
| 983 | |
| 984 | /* Write power on to DPCD */ |
| 985 | data = DP_SET_POWER_D0; |
| 986 | retry = 0; |
| 987 | do { |
| 988 | ret = tegra_dc_dp_dpcd_write(priv, DP_SET_POWER, data); |
| 989 | } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret); |
| 990 | |
| 991 | if (ret || retry >= DP_POWER_ON_MAX_TRIES) { |
| 992 | debug("dp: failed to power on panel (0x%x)\n", ret); |
| 993 | return -ENETUNREACH; |
| 994 | goto error_enable; |
| 995 | } |
| 996 | |
| 997 | /* Confirm DP plugging status */ |
| 998 | if (!(tegra_dpaux_readl(priv, DPAUX_DP_AUXSTAT) & |
| 999 | DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { |
| 1000 | debug("dp: could not detect HPD\n"); |
| 1001 | return -ENXIO; |
| 1002 | } |
| 1003 | |
| 1004 | /* Check DP version */ |
| 1005 | if (tegra_dc_dp_dpcd_read(priv, DP_DPCD_REV, &priv->revision)) { |
| 1006 | debug("dp: failed to read the revision number from sink\n"); |
| 1007 | return -EIO; |
| 1008 | } |
| 1009 | |
| 1010 | if (tegra_dc_dp_explore_link_cfg(priv, link_cfg, sor, timing)) { |
| 1011 | debug("dp: error configuring link\n"); |
| 1012 | return -ENOMEDIUM; |
| 1013 | } |
| 1014 | |
| 1015 | tegra_dc_sor_set_power_state(sor, 1); |
| 1016 | ret = tegra_dc_sor_attach(sor, link_cfg, timing); |
| 1017 | if (ret && ret != -EEXIST) |
| 1018 | return ret; |
| 1019 | |
| 1020 | /* Power down the unused lanes to save power - a few hundred mW */ |
| 1021 | tegra_dc_sor_power_down_unused_lanes(sor, link_cfg); |
| 1022 | |
| 1023 | priv->enabled = true; |
| 1024 | error_enable: |
| 1025 | return 0; |
| 1026 | } |
| 1027 | |
| 1028 | static int tegra_dp_ofdata_to_platdata(struct udevice *dev) |
| 1029 | { |
| 1030 | struct tegra_dp_plat *plat = dev_get_platdata(dev); |
| 1031 | const void *blob = gd->fdt_blob; |
| 1032 | |
| 1033 | plat->base = fdtdec_get_addr(blob, dev->of_offset, "reg"); |
| 1034 | |
| 1035 | return 0; |
| 1036 | } |
| 1037 | |
| 1038 | static int tegra_dp_read_edid(struct udevice *dev, u8 *buf, int buf_size) |
| 1039 | { |
| 1040 | struct tegra_dp_priv *priv = dev_get_priv(dev); |
| 1041 | const int tegra_edid_i2c_address = 0x50; |
| 1042 | u32 aux_stat = 0; |
| 1043 | |
| 1044 | tegra_dc_dpaux_enable(priv); |
| 1045 | |
| 1046 | return tegra_dc_i2c_aux_read(priv, tegra_edid_i2c_address, 0, buf, |
| 1047 | buf_size, &aux_stat); |
| 1048 | } |
| 1049 | |
| 1050 | static const struct dm_display_port_ops dp_tegra_ops = { |
| 1051 | .read_edid = tegra_dp_read_edid, |
| 1052 | .enable = tegra_dp_enable, |
| 1053 | }; |
| 1054 | |
| 1055 | static int dp_tegra_probe(struct udevice *dev) |
| 1056 | { |
| 1057 | struct tegra_dp_plat *plat = dev_get_platdata(dev); |
| 1058 | struct tegra_dp_priv *priv = dev_get_priv(dev); |
| 1059 | |
| 1060 | priv->regs = (struct dpaux_ctlr *)plat->base; |
| 1061 | priv->enabled = false; |
| 1062 | |
| 1063 | return 0; |
| 1064 | } |
| 1065 | |
| 1066 | static const struct udevice_id tegra_dp_ids[] = { |
| 1067 | { .compatible = "nvidia,tegra124-dpaux" }, |
| 1068 | { } |
| 1069 | }; |
| 1070 | |
| 1071 | U_BOOT_DRIVER(dp_tegra) = { |
| 1072 | .name = "dpaux_tegra", |
| 1073 | .id = UCLASS_DISPLAY_PORT, |
| 1074 | .of_match = tegra_dp_ids, |
| 1075 | .ofdata_to_platdata = tegra_dp_ofdata_to_platdata, |
| 1076 | .probe = dp_tegra_probe, |
| 1077 | .ops = &dp_tegra_ops, |
| 1078 | .priv_auto_alloc_size = sizeof(struct tegra_dp_priv), |
| 1079 | .platdata_auto_alloc_size = sizeof(struct tegra_dp_plat), |
| 1080 | }; |