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Tom Warrenb2871032012-12-11 13:34:15 +00001/*
Tom Warrenf29f0862013-01-23 14:01:01 -07002 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
Tom Warrenb2871032012-12-11 13:34:15 +00003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra30 Clock control functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/clock.h>
22#include <asm/arch/tegra.h>
23#include <asm/arch-tegra/clk_rst.h>
24#include <asm/arch-tegra/timer.h>
25#include <div64.h>
26#include <fdtdec.h>
27
28/*
Tom Warrenf29f0862013-01-23 14:01:01 -070029 * Clock types that we can use as a source. The Tegra30 has muxes for the
Tom Warrenb2871032012-12-11 13:34:15 +000030 * peripheral clocks, and in most cases there are four options for the clock
31 * source. This gives us a clock 'type' and exploits what commonality exists
32 * in the device.
33 *
34 * Letters are obvious, except for T which means CLK_M, and S which means the
35 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
36 * datasheet) and PLL_M are different things. The former is the basic
37 * clock supplied to the SOC from an external oscillator. The latter is the
38 * memory clock PLL.
39 *
40 * See definitions in clock_id in the header file.
41 */
42enum clock_type_id {
43 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
44 CLOCK_TYPE_MCPA, /* and so on */
45 CLOCK_TYPE_MCPT,
46 CLOCK_TYPE_PCM,
47 CLOCK_TYPE_PCMT,
Tom Warren619bd992012-12-21 15:02:45 -070048 CLOCK_TYPE_PCMT16,
Tom Warrenb2871032012-12-11 13:34:15 +000049 CLOCK_TYPE_PDCT,
50 CLOCK_TYPE_ACPT,
51 CLOCK_TYPE_ASPTE,
52 CLOCK_TYPE_PMDACD2T,
53 CLOCK_TYPE_PCST,
54
55 CLOCK_TYPE_COUNT,
Tom Warrenf29f0862013-01-23 14:01:01 -070056 CLOCK_TYPE_NONE = -1, /* invalid clock type */
Tom Warrenb2871032012-12-11 13:34:15 +000057};
58
59enum {
Tom Warrenf29f0862013-01-23 14:01:01 -070060 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
61};
62
Tom Warrenb2871032012-12-11 13:34:15 +000063/*
64 * Clock source mux for each clock type. This just converts our enum into
65 * a list of mux sources for use by the code.
66 *
67 * Note:
68 * The extra column in each clock source array is used to store the mask
69 * bits in its register for the source.
70 */
71#define CLK(x) CLOCK_ID_ ## x
72static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
Tom Warrenf29f0862013-01-23 14:01:01 -070073 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000075 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070076 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000078 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070079 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000081 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070082 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000084 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070085 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000087 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070088 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warren619bd992012-12-21 15:02:45 -070090 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070091 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
92 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000093 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070094 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000096 MASK_BITS_31_30},
Tom Warrenf29f0862013-01-23 14:01:01 -070097 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
98 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +000099 MASK_BITS_31_29},
Tom Warrenf29f0862013-01-23 14:01:01 -0700100 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
101 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000102 MASK_BITS_31_29},
Tom Warrenf29f0862013-01-23 14:01:01 -0700103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
104 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Stephen Warren5916a362014-01-24 10:16:18 -0700105 MASK_BITS_31_28}
Tom Warrenb2871032012-12-11 13:34:15 +0000106};
107
Tom Warrenb2871032012-12-11 13:34:15 +0000108/*
109 * Clock type for each peripheral clock source. We put the name in each
110 * record just so it is easy to match things up
111 */
112#define TYPE(name, type) type
113static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
114 /* 0x00 */
115 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700116 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
117 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
118 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
119 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
120 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
121 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
122 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000123
124 /* 0x08 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700125 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
126 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
127 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
128 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
129 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
130 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
131 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
132 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
Tom Warrenb2871032012-12-11 13:34:15 +0000133
134 /* 0x10 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700135 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
136 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000137 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
Tom Warrenf29f0862013-01-23 14:01:01 -0700138 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
139 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000140 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
141 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
142 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
143
144 /* 0x18 */
145 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
146 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700147 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
148 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
149 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
150 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
151 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
152 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000153
154 /* 0x20 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700155 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
156 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
157 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
158 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
159 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
160 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
161 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
Tom Warrenb2871032012-12-11 13:34:15 +0000162 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
163
164 /* 0x28 */
165 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
166 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
167 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
Tom Warrenf29f0862013-01-23 14:01:01 -0700168 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
169 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
170 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
171 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
172 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000173
174 /* 0x30 */
175 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
176 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
177 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700178 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
179 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
180 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
181 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
182 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000183
Tom Warrenf29f0862013-01-23 14:01:01 -0700184 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
185 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
186 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
187 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
188 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
189 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
190 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
191 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
192 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000193
194 /* 0x40 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700195 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
196 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
197 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
198 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
199 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
Tom Warrenb2871032012-12-11 13:34:15 +0000200 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
Tom Warrenf29f0862013-01-23 14:01:01 -0700201 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
Tom Warrenb2871032012-12-11 13:34:15 +0000202 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
203
204 /* 0x48 */
205 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
206 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
Tom Warrenf29f0862013-01-23 14:01:01 -0700207 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
208 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
209 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
211 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tom Warrenb2871032012-12-11 13:34:15 +0000213
214 /* 0x50 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700215 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
216 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
219 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
220 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
221 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
Tom Warrenb2871032012-12-11 13:34:15 +0000222};
223
224/*
225 * This array translates a periph_id to a periphc_internal_id
226 *
227 * Not present/matched up:
228 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
229 * SPDIF - which is both 0x08 and 0x0c
230 *
231 */
232#define NONE(name) (-1)
233#define OFFSET(name, value) PERIPHC_ ## name
234static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
235 /* Low word: 31:0 */
236 NONE(CPU),
237 NONE(COP),
238 NONE(TRIGSYS),
239 NONE(RESERVED3),
240 NONE(RESERVED4),
241 NONE(TMR),
242 PERIPHC_UART1,
Tom Warrenf29f0862013-01-23 14:01:01 -0700243 PERIPHC_UART2, /* and vfir 0x68 */
Tom Warrenb2871032012-12-11 13:34:15 +0000244
245 /* 8 */
246 NONE(GPIO),
247 PERIPHC_SDMMC2,
Tom Warrenf29f0862013-01-23 14:01:01 -0700248 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
Tom Warrenb2871032012-12-11 13:34:15 +0000249 PERIPHC_I2S1,
250 PERIPHC_I2C1,
251 PERIPHC_NDFLASH,
252 PERIPHC_SDMMC1,
253 PERIPHC_SDMMC4,
254
255 /* 16 */
256 NONE(RESERVED16),
257 PERIPHC_PWM,
258 PERIPHC_I2S2,
259 PERIPHC_EPP,
260 PERIPHC_VI,
261 PERIPHC_G2D,
262 NONE(USBD),
263 NONE(ISP),
264
265 /* 24 */
266 PERIPHC_G3D,
267 NONE(RESERVED25),
268 PERIPHC_DISP2,
269 PERIPHC_DISP1,
270 PERIPHC_HOST1X,
271 NONE(VCP),
272 PERIPHC_I2S0,
273 NONE(CACHE2),
274
275 /* Middle word: 63:32 */
276 NONE(MEM),
277 NONE(AHBDMA),
278 NONE(APBDMA),
279 NONE(RESERVED35),
280 NONE(RESERVED36),
281 NONE(STAT_MON),
282 NONE(RESERVED38),
283 NONE(RESERVED39),
284
285 /* 40 */
286 NONE(KFUSE),
Allen Martin7d54f022013-01-29 13:51:25 +0000287 PERIPHC_SBC1,
Tom Warrenb2871032012-12-11 13:34:15 +0000288 PERIPHC_NOR,
289 NONE(RESERVED43),
290 PERIPHC_SBC2,
291 NONE(RESERVED45),
292 PERIPHC_SBC3,
293 PERIPHC_DVC_I2C,
294
295 /* 48 */
296 NONE(DSI),
Tom Warrenf29f0862013-01-23 14:01:01 -0700297 PERIPHC_TVO, /* also CVE 0x40 */
Tom Warrenb2871032012-12-11 13:34:15 +0000298 PERIPHC_MIPI,
299 PERIPHC_HDMI,
300 NONE(CSI),
301 PERIPHC_TVDAC,
302 PERIPHC_I2C2,
303 PERIPHC_UART3,
304
305 /* 56 */
306 NONE(RESERVED56),
307 PERIPHC_EMC,
308 NONE(USB2),
309 NONE(USB3),
310 PERIPHC_MPE,
311 PERIPHC_VDE,
312 NONE(BSEA),
313 NONE(BSEV),
314
315 /* Upper word 95:64 */
316 PERIPHC_SPEEDO,
317 PERIPHC_UART4,
318 PERIPHC_UART5,
319 PERIPHC_I2C3,
320 PERIPHC_SBC4,
321 PERIPHC_SDMMC3,
322 NONE(PCIE),
323 PERIPHC_OWR,
324
325 /* 72 */
326 NONE(AFI),
327 PERIPHC_CSITE,
328 NONE(PCIEXCLK),
329 NONE(AVPUCQ),
330 NONE(RESERVED76),
331 NONE(RESERVED77),
332 NONE(RESERVED78),
333 NONE(DTV),
334
335 /* 80 */
336 PERIPHC_NANDSPEED,
337 PERIPHC_I2CSLOW,
338 NONE(DSIB),
339 NONE(RESERVED83),
340 NONE(IRAMA),
341 NONE(IRAMB),
342 NONE(IRAMC),
343 NONE(IRAMD),
344
345 /* 88 */
346 NONE(CRAM2),
347 NONE(RESERVED89),
348 NONE(MDOUBLER),
349 NONE(RESERVED91),
350 NONE(SUSOUT),
351 NONE(RESERVED93),
352 NONE(RESERVED94),
353 NONE(RESERVED95),
354
355 /* V word: 31:0 */
356 NONE(CPUG),
357 NONE(CPULP),
358 PERIPHC_G3D2,
359 PERIPHC_MSELECT,
360 PERIPHC_TSENSOR,
361 PERIPHC_I2S3,
362 PERIPHC_I2S4,
363 PERIPHC_I2C4,
364
365 /* 08 */
366 PERIPHC_SBC5,
367 PERIPHC_SBC6,
368 PERIPHC_AUDIO,
369 NONE(APBIF),
370 PERIPHC_DAM0,
371 PERIPHC_DAM1,
372 PERIPHC_DAM2,
373 PERIPHC_HDA2CODEC2X,
374
375 /* 16 */
376 NONE(ATOMICS),
377 NONE(RESERVED17),
378 NONE(RESERVED18),
379 NONE(RESERVED19),
380 NONE(RESERVED20),
381 NONE(RESERVED21),
382 NONE(RESERVED22),
383 PERIPHC_ACTMON,
384
385 /* 24 */
386 NONE(RESERVED24),
387 NONE(RESERVED25),
388 NONE(RESERVED26),
389 NONE(RESERVED27),
390 PERIPHC_SATA,
391 PERIPHC_HDA,
392 NONE(RESERVED30),
393 NONE(RESERVED31),
394
395 /* W word: 31:0 */
396 NONE(HDA2HDMICODEC),
397 NONE(SATACOLD),
398 NONE(RESERVED0_PCIERX0),
399 NONE(RESERVED1_PCIERX1),
400 NONE(RESERVED2_PCIERX2),
401 NONE(RESERVED3_PCIERX3),
402 NONE(RESERVED4_PCIERX4),
403 NONE(RESERVED5_PCIERX5),
404
405 /* 40 */
406 NONE(CEC),
407 NONE(RESERVED6_PCIE2),
408 NONE(RESERVED7_EMC),
409 NONE(RESERVED8_HDMI),
410 NONE(RESERVED9_SATA),
411 NONE(RESERVED10_MIPI),
412 NONE(EX_RESERVED46),
413 NONE(EX_RESERVED47),
414};
415
416/*
417 * Get the oscillator frequency, from the corresponding hardware configuration
Tom Warrenf29f0862013-01-23 14:01:01 -0700418 * field. Note that T30 supports 3 new higher freqs, but we map back
419 * to the old T20 freqs. Support for the higher oscillators is TBD.
Tom Warrenb2871032012-12-11 13:34:15 +0000420 */
421enum clock_osc_freq clock_get_osc_freq(void)
422{
423 struct clk_rst_ctlr *clkrst =
424 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
425 u32 reg;
426
427 reg = readl(&clkrst->crc_osc_ctrl);
Tom Warrenf29f0862013-01-23 14:01:01 -0700428 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
Tom Warrenb2871032012-12-11 13:34:15 +0000429
Tom Warrenf29f0862013-01-23 14:01:01 -0700430 if (reg & 1) /* one of the newer freqs */
431 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
Tom Warrenb2871032012-12-11 13:34:15 +0000432
Tom Warrenf29f0862013-01-23 14:01:01 -0700433 return reg >> 2; /* Map to most common (T20) freqs */
Tom Warrenb2871032012-12-11 13:34:15 +0000434}
435
436/* Returns a pointer to the clock source register for a peripheral */
Tom Warrenf29f0862013-01-23 14:01:01 -0700437u32 *get_periph_source_reg(enum periph_id periph_id)
Tom Warrenb2871032012-12-11 13:34:15 +0000438{
439 struct clk_rst_ctlr *clkrst =
Tom Warrenf29f0862013-01-23 14:01:01 -0700440 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
Tom Warrenb2871032012-12-11 13:34:15 +0000441 enum periphc_internal_id internal_id;
442
443 /* Coresight is a special case */
444 if (periph_id == PERIPH_ID_CSI)
445 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
446
447 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
448 internal_id = periph_id_to_internal_id[periph_id];
449 assert(internal_id != -1);
450 if (internal_id >= PERIPHC_VW_FIRST) {
451 internal_id -= PERIPHC_VW_FIRST;
452 return &clkrst->crc_clk_src_vw[internal_id];
453 } else
454 return &clkrst->crc_clk_src[internal_id];
455}
456
Tom Warrenb2871032012-12-11 13:34:15 +0000457/**
458 * Given a peripheral ID and the required source clock, this returns which
459 * value should be programmed into the source mux for that peripheral.
460 *
461 * There is special code here to handle the one source type with 5 sources.
462 *
463 * @param periph_id peripheral to start
464 * @param source PLL id of required parent clock
465 * @param mux_bits Set to number of bits in mux register: 2 or 4
Tom Warrenf29f0862013-01-23 14:01:01 -0700466 * @param divider_bits Set to number of divider bits (8 or 16)
Tom Warrenb2871032012-12-11 13:34:15 +0000467 * @return mux value (0-4, or -1 if not found)
468 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700469int get_periph_clock_source(enum periph_id periph_id,
470 enum clock_id parent, int *mux_bits, int *divider_bits)
Tom Warrenb2871032012-12-11 13:34:15 +0000471{
472 enum clock_type_id type;
473 enum periphc_internal_id internal_id;
474 int mux;
475
476 assert(clock_periph_id_isvalid(periph_id));
477
478 internal_id = periph_id_to_internal_id[periph_id];
479 assert(periphc_internal_id_isvalid(internal_id));
480
481 type = clock_periph_type[internal_id];
482 assert(clock_type_id_isvalid(type));
483
484 *mux_bits = clock_source[type][CLOCK_MAX_MUX];
485
Tom Warren619bd992012-12-21 15:02:45 -0700486 if (type == CLOCK_TYPE_PCMT16)
487 *divider_bits = 16;
488 else
489 *divider_bits = 8;
490
Tom Warrenb2871032012-12-11 13:34:15 +0000491 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
492 if (clock_source[type][mux] == parent)
493 return mux;
494
495 /* if we get here, either us or the caller has made a mistake */
496 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
497 parent);
498 return -1;
499}
500
Tom Warrenb2871032012-12-11 13:34:15 +0000501void clock_set_enable(enum periph_id periph_id, int enable)
502{
503 struct clk_rst_ctlr *clkrst =
504 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
505 u32 *clk;
506 u32 reg;
507
508 /* Enable/disable the clock to this peripheral */
509 assert(clock_periph_id_isvalid(periph_id));
510 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
511 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
512 else
513 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
514 reg = readl(clk);
515 if (enable)
516 reg |= PERIPH_MASK(periph_id);
517 else
518 reg &= ~PERIPH_MASK(periph_id);
519 writel(reg, clk);
520}
521
Tom Warrenb2871032012-12-11 13:34:15 +0000522void reset_set_enable(enum periph_id periph_id, int enable)
523{
524 struct clk_rst_ctlr *clkrst =
525 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
526 u32 *reset;
527 u32 reg;
528
529 /* Enable/disable reset to the peripheral */
530 assert(clock_periph_id_isvalid(periph_id));
531 if (periph_id < PERIPH_ID_VW_FIRST)
532 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
533 else
534 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
535 reg = readl(reset);
536 if (enable)
537 reg |= PERIPH_MASK(periph_id);
538 else
539 reg &= ~PERIPH_MASK(periph_id);
540 writel(reg, reset);
541}
542
Tom Warrenb2871032012-12-11 13:34:15 +0000543#ifdef CONFIG_OF_CONTROL
544/*
545 * Convert a device tree clock ID to our peripheral ID. They are mostly
546 * the same but we are very cautious so we check that a valid clock ID is
547 * provided.
548 *
Tom Warren619bd992012-12-21 15:02:45 -0700549 * @param clk_id Clock ID according to tegra30 device tree binding
Tom Warrenb2871032012-12-11 13:34:15 +0000550 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
551 */
Tom Warrenf29f0862013-01-23 14:01:01 -0700552enum periph_id clk_id_to_periph_id(int clk_id)
Tom Warrenb2871032012-12-11 13:34:15 +0000553{
Tom Warren619bd992012-12-21 15:02:45 -0700554 if (clk_id > PERIPH_ID_COUNT)
Tom Warrenb2871032012-12-11 13:34:15 +0000555 return PERIPH_ID_NONE;
556
557 switch (clk_id) {
Tom Warren619bd992012-12-21 15:02:45 -0700558 case PERIPH_ID_RESERVED3:
559 case PERIPH_ID_RESERVED4:
560 case PERIPH_ID_RESERVED16:
561 case PERIPH_ID_RESERVED24:
562 case PERIPH_ID_RESERVED35:
563 case PERIPH_ID_RESERVED43:
564 case PERIPH_ID_RESERVED45:
565 case PERIPH_ID_RESERVED56:
566 case PERIPH_ID_RESERVED76:
567 case PERIPH_ID_RESERVED77:
568 case PERIPH_ID_RESERVED78:
569 case PERIPH_ID_RESERVED83:
570 case PERIPH_ID_RESERVED89:
571 case PERIPH_ID_RESERVED91:
572 case PERIPH_ID_RESERVED93:
573 case PERIPH_ID_RESERVED94:
574 case PERIPH_ID_RESERVED95:
Tom Warrenb2871032012-12-11 13:34:15 +0000575 return PERIPH_ID_NONE;
576 default:
577 return clk_id;
578 }
579}
Tom Warrenb2871032012-12-11 13:34:15 +0000580#endif /* CONFIG_OF_CONTROL */
581
Tom Warrenb2871032012-12-11 13:34:15 +0000582void clock_early_init(void)
583{
584 /*
585 * PLLP output frequency set to 408Mhz
586 * PLLC output frequency set to 228Mhz
587 */
588 switch (clock_get_osc_freq()) {
589 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
590 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
591 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
592 break;
593
594 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
595 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
596 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
597 break;
598
599 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
600 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
601 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
602 break;
603 case CLOCK_OSC_FREQ_19_2:
604 default:
605 /*
606 * These are not supported. It is too early to print a
607 * message and the UART likely won't work anyway due to the
608 * oscillator being wrong.
609 */
610 break;
611 }
612}
Tom Warrenb40f7342013-04-01 15:48:54 -0700613
614void arch_timer_init(void)
615{
616}