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York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
York Sunee52b182012-10-11 07:13:37 +00005 */
6
7#include <common.h>
8#include <i2c.h>
9#include <hwconfig.h>
10#include <asm/mmu.h>
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
York Sunee52b182012-10-11 07:13:37 +000013#include <asm/fsl_law.h>
York Sun1cb19fb2013-06-27 10:48:29 -070014#include "ddr.h"
York Sunee52b182012-10-11 07:13:37 +000015
16DECLARE_GLOBAL_DATA_PTR;
17
York Sunee52b182012-10-11 07:13:37 +000018void fsl_ddr_board_options(memctl_options_t *popts,
19 dimm_params_t *pdimm,
20 unsigned int ctrl_num)
21{
22 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23 ulong ddr_freq;
24
25 if (ctrl_num > 2) {
26 printf("Not supported controller number %d\n", ctrl_num);
27 return;
28 }
29 if (!pdimm->n_ranks)
30 return;
31
32 /*
33 * we use identical timing for all slots. If needed, change the code
34 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
35 */
36 if (popts->registered_dimm_en)
37 pbsp = rdimms[0];
38 else
39 pbsp = udimms[0];
40
41
42 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
43 * freqency and n_banks specified in board_specific_parameters table.
44 */
45 ddr_freq = get_ddr_freq(0) / 1000000;
46 while (pbsp->datarate_mhz_high) {
York Sun054dfd92013-03-25 07:33:19 +000047 if (pbsp->n_ranks == pdimm->n_ranks &&
48 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
York Sunee52b182012-10-11 07:13:37 +000049 if (ddr_freq <= pbsp->datarate_mhz_high) {
50 popts->cpo_override = pbsp->cpo;
51 popts->write_data_delay =
52 pbsp->write_data_delay;
53 popts->clk_adjust = pbsp->clk_adjust;
54 popts->wrlvl_start = pbsp->wrlvl_start;
55 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
56 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
Priyanka Jain0dd38a32013-09-25 10:41:19 +053057 popts->twot_en = pbsp->force_2t;
York Sunee52b182012-10-11 07:13:37 +000058 goto found;
59 }
60 pbsp_highest = pbsp;
61 }
62 pbsp++;
63 }
64
65 if (pbsp_highest) {
66 printf("Error: board specific timing not found "
67 "for data rate %lu MT/s\n"
68 "Trying to use the highest speed (%u) parameters\n",
69 ddr_freq, pbsp_highest->datarate_mhz_high);
70 popts->cpo_override = pbsp_highest->cpo;
71 popts->write_data_delay = pbsp_highest->write_data_delay;
72 popts->clk_adjust = pbsp_highest->clk_adjust;
73 popts->wrlvl_start = pbsp_highest->wrlvl_start;
74 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
75 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
Priyanka Jain0dd38a32013-09-25 10:41:19 +053076 popts->twot_en = pbsp_highest->force_2t;
York Sunee52b182012-10-11 07:13:37 +000077 } else {
78 panic("DIMM is not supported by this board");
79 }
80found:
York Sun054dfd92013-03-25 07:33:19 +000081 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
82 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
83 "wrlvl_ctrl_3 0x%x\n",
84 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
85 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
86 pbsp->wrlvl_ctl_3);
87
York Sunee52b182012-10-11 07:13:37 +000088 /*
89 * Factors to consider for half-strength driver enable:
90 * - number of DIMMs installed
91 */
92 popts->half_strength_driver_enable = 0;
93 /*
94 * Write leveling override
95 */
96 popts->wrlvl_override = 1;
97 popts->wrlvl_sample = 0xf;
98
99 /*
100 * Rtt and Rtt_WR override
101 */
102 popts->rtt_override = 0;
103
104 /* Enable ZQ calibration */
105 popts->zq_en = 1;
106
107 /* DHC_EN =1, ODT = 75 Ohm */
108 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
109 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
110}
111
112phys_size_t initdram(int board_type)
113{
114 phys_size_t dram_size;
115
116 puts("Initializing....using SPD\n");
117
Shaohui Xieb6036992014-04-22 15:10:44 +0800118#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
York Sunee52b182012-10-11 07:13:37 +0000119 dram_size = fsl_ddr_sdram();
120
121 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
122 dram_size *= 0x100000;
123
Shaohui Xieb6036992014-04-22 15:10:44 +0800124#else
125 /* DDR has been initialised by first stage boot loader */
126 dram_size = fsl_ddr_sdram_size();
127#endif
York Sunee52b182012-10-11 07:13:37 +0000128 return dram_size;
129}