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Przemyslaw Marczak5d387d02015-05-13 13:38:32 +02001/*
2 * Copyright (C) 2015 Samsung Electronics
3 * Przemyslaw Marczak <p.marczak@samsung.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _SANDBOX_PMIC_H_
9#define _SANDBOX_PMIC_H_
10
11#define SANDBOX_LDO_DRIVER "sandbox_ldo"
12#define SANDBOX_OF_LDO_PREFIX "ldo"
13#define SANDBOX_BUCK_DRIVER "sandbox_buck"
14#define SANDBOX_OF_BUCK_PREFIX "buck"
15
16#define SANDBOX_BUCK_COUNT 2
17#define SANDBOX_LDO_COUNT 2
18/*
19 * Sandbox PMIC registers:
20 * We have only 12 significant registers, but we alloc 16 for padding.
21 */
22enum {
23 SANDBOX_PMIC_REG_BUCK1_UV = 0,
24 SANDBOX_PMIC_REG_BUCK1_UA,
25 SANDBOX_PMIC_REG_BUCK1_OM,
26
27 SANDBOX_PMIC_REG_BUCK2_UV,
28 SANDBOX_PMIC_REG_BUCK2_UA,
29 SANDBOX_PMIC_REG_BUCK2_OM,
30
31 SANDBOX_PMIC_REG_LDO_OFFSET,
32 SANDBOX_PMIC_REG_LDO1_UV = SANDBOX_PMIC_REG_LDO_OFFSET,
33 SANDBOX_PMIC_REG_LDO1_UA,
34 SANDBOX_PMIC_REG_LDO1_OM,
35
36 SANDBOX_PMIC_REG_LDO2_UV,
37 SANDBOX_PMIC_REG_LDO2_UA,
38 SANDBOX_PMIC_REG_LDO2_OM,
39
40 SANDBOX_PMIC_REG_COUNT = 16,
41};
42
43/* Register offset for output: micro Volts, micro Amps, Operation Mode */
44enum {
45 OUT_REG_UV = 0,
46 OUT_REG_UA,
47 OUT_REG_OM,
48 OUT_REG_COUNT,
49};
50
51/* Buck operation modes */
52enum {
53 BUCK_OM_OFF = 0,
54 BUCK_OM_ON,
55 BUCK_OM_PWM,
56 BUCK_OM_COUNT,
57};
58
59/* Ldo operation modes */
60enum {
61 LDO_OM_OFF = 0,
62 LDO_OM_ON,
63 LDO_OM_SLEEP,
64 LDO_OM_STANDBY,
65 LDO_OM_COUNT,
66};
67
68/* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
69#define OUT_BUCK1_UV_MIN 800000
70#define OUT_BUCK1_UV_MAX 2400000
71#define OUT_BUCK1_UV_STEP 25000
72
73/* BUCK1 Amperage: min: 150mA, step: 25mA, max: 250mA */
74#define OUT_BUCK1_UA_MIN 150000
75#define OUT_BUCK1_UA_MAX 250000
76#define OUT_BUCK1_UA_STEP 25000
77
78/* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
79#define OUT_BUCK2_UV_MIN 750000
80#define OUT_BUCK2_UV_MAX 3950000
81#define OUT_BUCK2_UV_STEP 50000
82
83/* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
84#define OUT_LDO1_UV_MIN 800000
85#define OUT_LDO1_UV_MAX 2400000
86#define OUT_LDO1_UV_STEP 25000
87
88/* LDO1 Amperage: min: 100mA, step: 50mA, max: 200mA */
89#define OUT_LDO1_UA_MIN 100000
90#define OUT_LDO1_UA_MAX 200000
91#define OUT_LDO1_UA_STEP 50000
92
93/* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
94#define OUT_LDO2_UV_MIN 750000
95#define OUT_LDO2_UV_MAX 3950000
96#define OUT_LDO2_UV_STEP 50000
97
98/* register <-> value conversion */
99#define REG2VAL(min, step, reg) ((min) + ((step) * (reg)))
100#define VAL2REG(min, step, val) (((val) - (min)) / (step))
101
102/* Operation mode id -> register value conversion */
103#define OM2REG(x) (x)
104
Przemyslaw Marczake8f339e2015-05-13 13:38:33 +0200105/* Test data for: test/dm/power.c */
106
107/* BUCK names */
108#define SANDBOX_BUCK1_DEVNAME "buck1"
109#define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V"
110#define SANDBOX_BUCK2_DEVNAME "buck2"
111#define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V"
112/* LDO names */
113#define SANDBOX_LDO1_DEVNAME "ldo1"
114#define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V"
115#define SANDBOX_LDO2_DEVNAME "ldo2"
116#define SANDBOX_LDO2_PLATNAME "VDD_LCD_3.3V"
117
118/*
119 * Expected regulators setup after call of:
Simon Glass3b55d302015-06-23 15:38:58 -0600120 * - regulator_autoset_by_name()
Przemyslaw Marczake8f339e2015-05-13 13:38:33 +0200121 * - regulator_list_autoset()
122 */
123
Simon Glass3b55d302015-06-23 15:38:58 -0600124/* BUCK1: for testing regulator_autoset_by_name() */
Przemyslaw Marczake8f339e2015-05-13 13:38:33 +0200125#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UV 1200000
126#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA 200000
127#define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE true
128
129/* LDO1/2 for testing regulator_list_autoset() */
130#define SANDBOX_LDO1_AUTOSET_EXPECTED_UV 1800000
131#define SANDBOX_LDO1_AUTOSET_EXPECTED_UA 100000
132#define SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE true
133
134#define SANDBOX_LDO2_AUTOSET_EXPECTED_UV 3000000
135#define SANDBOX_LDO2_AUTOSET_EXPECTED_UA -ENOSYS
136#define SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE false
137
Przemyslaw Marczak5d387d02015-05-13 13:38:32 +0200138#endif