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gerrit.cesnet.cz / github / trini / u-boot / 57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2 / . / arch / powerpc / cpu / mpc8xxx / ddr / interactive.c
blob: cb71f94ba1ecd1540728892dc0bf3c72d3b1f94c [file] [log] [blame]
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1/*
York Sun73b53962012-08-17 08:22:37 +0000[diff] [blame]2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or any later versionas published by the Free Software Foundation.
7 */
8
9/*
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
13 * York Sun [at freescale.com]
14 */
15
16#include <common.h>
17#include <linux/ctype.h>
18#include <asm/types.h>
19
20#include <asm/fsl_ddr_sdram.h>
21#include "ddr.h"
22
23/* Option parameter Structures */
24struct options_string {
25 const char *option_name;
26 size_t offset;
27 unsigned int size;
28 const char printhex;
29};
30
31static unsigned int picos_to_mhz(unsigned int picos)
32{
33 return 1000000 / picos;
34}
35
36static void print_option_table(const struct options_string *table,
37 int table_size,
38 const void *base)
39{
40 unsigned int i;
41 unsigned int *ptr;
42 unsigned long long *ptr_l;
43
44 for (i = 0; i < table_size; i++) {
45 switch (table[i].size) {
46 case 4:
47 ptr = (unsigned int *) (base + table[i].offset);
48 if (table[i].printhex) {
49 printf("%s = 0x%08X\n",
50 table[i].option_name, *ptr);
51 } else {
52 printf("%s = %u\n",
53 table[i].option_name, *ptr);
54 }
55 break;
56 case 8:
57 ptr_l = (unsigned long long *) (base + table[i].offset);
58 printf("%s = %llu\n",
59 table[i].option_name, *ptr_l);
60 break;
61 default:
62 printf("Unrecognized size!\n");
63 break;
64 }
65 }
66}
67
68static int handle_option_table(const struct options_string *table,
69 int table_size,
70 void *base,
71 const char *opt,
72 const char *val)
73{
74 unsigned int i;
75 unsigned int value, *ptr;
76 unsigned long long value_l, *ptr_l;
77
78 for (i = 0; i < table_size; i++) {
79 if (strcmp(table[i].option_name, opt) != 0)
80 continue;
81 switch (table[i].size) {
82 case 4:
83 value = simple_strtoul(val, NULL, 0);
84 ptr = base + table[i].offset;
85 *ptr = value;
86 break;
87 case 8:
88 value_l = simple_strtoull(val, NULL, 0);
89 ptr_l = base + table[i].offset;
90 *ptr_l = value_l;
91 break;
92 default:
93 printf("Unrecognized size!\n");
94 break;
95 }
96 return 1;
97 }
98
99 return 0;
100}
101
102static void fsl_ddr_generic_edit(void *pdata,
103 void *pend,
104 unsigned int element_size,
105 unsigned int element_num,
106 unsigned int value)
107{
108 char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */
109
110 pcdata += element_num * element_size;
111 if ((pcdata + element_size) > (char *) pend) {
112 printf("trying to write past end of data\n");
113 return;
114 }
115
116 switch (element_size) {
117 case 1:
118 __raw_writeb(value, pcdata);
119 break;
120 case 2:
121 __raw_writew(value, pcdata);
122 break;
123 case 4:
124 __raw_writel(value, pcdata);
125 break;
126 default:
127 printf("unexpected element size %u\n", element_size);
128 break;
129 }
130}
131
132static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
133 unsigned int ctrl_num,
134 unsigned int dimm_num,
135 unsigned int element_num,
136 unsigned int value)
137{
138 generic_spd_eeprom_t *pspd;
139
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
141 fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
142}
143
144#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
145 sizeof((common_timing_params_t *)0)->x, 0}
146
147static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
148 unsigned int ctrl_num,
149 const char *optname_str,
150 const char *value_str)
151{
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
153
154 static const struct options_string options[] = {
155 COMMON_TIMING(tCKmin_X_ps),
156 COMMON_TIMING(tCKmax_ps),
157 COMMON_TIMING(tCKmax_max_ps),
158 COMMON_TIMING(tRCD_ps),
159 COMMON_TIMING(tRP_ps),
160 COMMON_TIMING(tRAS_ps),
161 COMMON_TIMING(tWR_ps),
162 COMMON_TIMING(tWTR_ps),
163 COMMON_TIMING(tRFC_ps),
164 COMMON_TIMING(tRRD_ps),
165 COMMON_TIMING(tRC_ps),
166 COMMON_TIMING(refresh_rate_ps),
167 COMMON_TIMING(tIS_ps),
168 COMMON_TIMING(tIH_ps),
169 COMMON_TIMING(tDS_ps),
170 COMMON_TIMING(tDH_ps),
171 COMMON_TIMING(tRTP_ps),
172 COMMON_TIMING(tDQSQ_max_ps),
173 COMMON_TIMING(tQHS_ps),
174 COMMON_TIMING(ndimms_present),
175 COMMON_TIMING(lowest_common_SPD_caslat),
176 COMMON_TIMING(highest_common_derated_caslat),
177 COMMON_TIMING(additive_latency),
178 COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
179 COMMON_TIMING(all_DIMMs_registered),
180 COMMON_TIMING(all_DIMMs_unbuffered),
181 COMMON_TIMING(all_DIMMs_ECC_capable),
182 COMMON_TIMING(total_mem),
183 COMMON_TIMING(base_address),
184 };
185 static const unsigned int n_opts = ARRAY_SIZE(options);
186
187 if (handle_option_table(options, n_opts, p, optname_str, value_str))
188 return;
189
190 printf("Error: couldn't find option string %s\n", optname_str);
191}
192
193#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
194 sizeof((dimm_params_t *)0)->x, 0}
195
196static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
197 unsigned int ctrl_num,
198 unsigned int dimm_num,
199 const char *optname_str,
200 const char *value_str)
201{
202 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
203
204 static const struct options_string options[] = {
205 DIMM_PARM(n_ranks),
206 DIMM_PARM(data_width),
207 DIMM_PARM(primary_sdram_width),
208 DIMM_PARM(ec_sdram_width),
209 DIMM_PARM(registered_dimm),
210
211 DIMM_PARM(n_row_addr),
212 DIMM_PARM(n_col_addr),
213 DIMM_PARM(edc_config),
214 DIMM_PARM(n_banks_per_sdram_device),
215 DIMM_PARM(burst_lengths_bitmask),
216 DIMM_PARM(row_density),
217
218 DIMM_PARM(tCKmin_X_ps),
219 DIMM_PARM(tCKmin_X_minus_1_ps),
220 DIMM_PARM(tCKmin_X_minus_2_ps),
221 DIMM_PARM(tCKmax_ps),
222
223 DIMM_PARM(caslat_X),
224 DIMM_PARM(caslat_X_minus_1),
225 DIMM_PARM(caslat_X_minus_2),
226
227 DIMM_PARM(caslat_lowest_derated),
228
229 DIMM_PARM(tRCD_ps),
230 DIMM_PARM(tRP_ps),
231 DIMM_PARM(tRAS_ps),
232 DIMM_PARM(tWR_ps),
233 DIMM_PARM(tWTR_ps),
234 DIMM_PARM(tRFC_ps),
235 DIMM_PARM(tRRD_ps),
236 DIMM_PARM(tRC_ps),
237 DIMM_PARM(refresh_rate_ps),
238
239 DIMM_PARM(tIS_ps),
240 DIMM_PARM(tIH_ps),
241 DIMM_PARM(tDS_ps),
242 DIMM_PARM(tDH_ps),
243 DIMM_PARM(tRTP_ps),
244 DIMM_PARM(tDQSQ_max_ps),
245 DIMM_PARM(tQHS_ps),
246
247 DIMM_PARM(rank_density),
248 DIMM_PARM(capacity),
249 DIMM_PARM(base_address),
250 };
251
252 static const unsigned int n_opts = ARRAY_SIZE(options);
253
254 if (handle_option_table(options, n_opts, p, optname_str, value_str))
255 return;
256
257 printf("couldn't find option string %s\n", optname_str);
258}
259
260static void print_dimm_parameters(const dimm_params_t *pdimm)
261{
262 static const struct options_string options[] = {
263 DIMM_PARM(n_ranks),
264 DIMM_PARM(data_width),
265 DIMM_PARM(primary_sdram_width),
266 DIMM_PARM(ec_sdram_width),
267 DIMM_PARM(registered_dimm),
268
269 DIMM_PARM(n_row_addr),
270 DIMM_PARM(n_col_addr),
271 DIMM_PARM(edc_config),
272 DIMM_PARM(n_banks_per_sdram_device),
273
274 DIMM_PARM(tCKmin_X_ps),
275 DIMM_PARM(tCKmin_X_minus_1_ps),
276 DIMM_PARM(tCKmin_X_minus_2_ps),
277 DIMM_PARM(tCKmax_ps),
278
279 DIMM_PARM(caslat_X),
280 DIMM_PARM(tAA_ps),
281 DIMM_PARM(caslat_X_minus_1),
282 DIMM_PARM(caslat_X_minus_2),
283 DIMM_PARM(caslat_lowest_derated),
284
285 DIMM_PARM(tRCD_ps),
286 DIMM_PARM(tRP_ps),
287 DIMM_PARM(tRAS_ps),
288 DIMM_PARM(tWR_ps),
289 DIMM_PARM(tWTR_ps),
290 DIMM_PARM(tRFC_ps),
291 DIMM_PARM(tRRD_ps),
292 DIMM_PARM(tRC_ps),
293 DIMM_PARM(refresh_rate_ps),
294
295 DIMM_PARM(tIS_ps),
296 DIMM_PARM(tIH_ps),
297 DIMM_PARM(tDS_ps),
298 DIMM_PARM(tDH_ps),
299 DIMM_PARM(tRTP_ps),
300 DIMM_PARM(tDQSQ_max_ps),
301 DIMM_PARM(tQHS_ps),
302 };
303 static const unsigned int n_opts = ARRAY_SIZE(options);
304
305 if (pdimm->n_ranks == 0) {
306 printf("DIMM not present\n");
307 return;
308 }
309 printf("DIMM organization parameters:\n");
310 printf("module part name = %s\n", pdimm->mpart);
311 printf("rank_density = %llu bytes (%llu megabytes)\n",
312 pdimm->rank_density, pdimm->rank_density / 0x100000);
313 printf("capacity = %llu bytes (%llu megabytes)\n",
314 pdimm->capacity, pdimm->capacity / 0x100000);
315 printf("burst_lengths_bitmask = %02X\n",
316 pdimm->burst_lengths_bitmask);
317 printf("base_addresss = %llu (%08llX %08llX)\n",
318 pdimm->base_address,
319 (pdimm->base_address >> 32),
320 pdimm->base_address & 0xFFFFFFFF);
321 print_option_table(options, n_opts, pdimm);
322}
323
324static void print_lowest_common_dimm_parameters(
325 const common_timing_params_t *plcd_dimm_params)
326{
327 static const struct options_string options[] = {
328 COMMON_TIMING(tCKmax_max_ps),
329 COMMON_TIMING(tRCD_ps),
330 COMMON_TIMING(tRP_ps),
331 COMMON_TIMING(tRAS_ps),
332 COMMON_TIMING(tWR_ps),
333 COMMON_TIMING(tWTR_ps),
334 COMMON_TIMING(tRFC_ps),
335 COMMON_TIMING(tRRD_ps),
336 COMMON_TIMING(tRC_ps),
337 COMMON_TIMING(refresh_rate_ps),
338 COMMON_TIMING(tIS_ps),
339 COMMON_TIMING(tDS_ps),
340 COMMON_TIMING(tDH_ps),
341 COMMON_TIMING(tRTP_ps),
342 COMMON_TIMING(tDQSQ_max_ps),
343 COMMON_TIMING(tQHS_ps),
344 COMMON_TIMING(lowest_common_SPD_caslat),
345 COMMON_TIMING(highest_common_derated_caslat),
346 COMMON_TIMING(additive_latency),
347 COMMON_TIMING(ndimms_present),
348 COMMON_TIMING(all_DIMMs_registered),
349 COMMON_TIMING(all_DIMMs_unbuffered),
350 COMMON_TIMING(all_DIMMs_ECC_capable),
351 };
352 static const unsigned int n_opts = ARRAY_SIZE(options);
353
354 /* Clock frequencies */
355 printf("tCKmin_X_ps = %u (%u MHz)\n",
356 plcd_dimm_params->tCKmin_X_ps,
357 picos_to_mhz(plcd_dimm_params->tCKmin_X_ps));
358 printf("tCKmax_ps = %u (%u MHz)\n",
359 plcd_dimm_params->tCKmax_ps,
360 picos_to_mhz(plcd_dimm_params->tCKmax_ps));
361 printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
362 plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
363
364 print_option_table(options, n_opts, plcd_dimm_params);
365
366 printf("total_mem = %llu (%llu megabytes)\n",
367 plcd_dimm_params->total_mem,
368 plcd_dimm_params->total_mem / 0x100000);
369 printf("base_address = %llu (%llu megabytes)\n",
370 plcd_dimm_params->base_address,
371 plcd_dimm_params->base_address / 0x100000);
372}
373
374#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
375 sizeof((memctl_options_t *)0)->x, 0}
376#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
377 offsetof(memctl_options_t, cs_local_opts[x].y), \
378 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
379
380static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
381 unsigned int ctl_num,
382 const char *optname_str,
383 const char *value_str)
384{
385 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
386 /*
387 * This array all on the stack and *computed* each time this
388 * function is rung.
389 */
390 static const struct options_string options[] = {
391 CTRL_OPTIONS_CS(0, odt_rd_cfg),
392 CTRL_OPTIONS_CS(0, odt_wr_cfg),
393#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
394 CTRL_OPTIONS_CS(1, odt_rd_cfg),
395 CTRL_OPTIONS_CS(1, odt_wr_cfg),
396#endif
397#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
398 CTRL_OPTIONS_CS(2, odt_rd_cfg),
399 CTRL_OPTIONS_CS(2, odt_wr_cfg),
400#endif
401#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
402 CTRL_OPTIONS_CS(3, odt_rd_cfg),
403 CTRL_OPTIONS_CS(3, odt_wr_cfg),
404#endif
405#if defined(CONFIG_FSL_DDR3)
406 CTRL_OPTIONS_CS(0, odt_rtt_norm),
407 CTRL_OPTIONS_CS(0, odt_rtt_wr),
408#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
409 CTRL_OPTIONS_CS(1, odt_rtt_norm),
410 CTRL_OPTIONS_CS(1, odt_rtt_wr),
411#endif
412#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
413 CTRL_OPTIONS_CS(2, odt_rtt_norm),
414 CTRL_OPTIONS_CS(2, odt_rtt_wr),
415#endif
416#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
417 CTRL_OPTIONS_CS(3, odt_rtt_norm),
418 CTRL_OPTIONS_CS(3, odt_rtt_wr),
419#endif
420#endif
421 CTRL_OPTIONS(memctl_interleaving),
422 CTRL_OPTIONS(memctl_interleaving_mode),
423 CTRL_OPTIONS(ba_intlv_ctl),
424 CTRL_OPTIONS(ECC_mode),
425 CTRL_OPTIONS(ECC_init_using_memctl),
426 CTRL_OPTIONS(DQS_config),
427 CTRL_OPTIONS(self_refresh_in_sleep),
428 CTRL_OPTIONS(dynamic_power),
429 CTRL_OPTIONS(data_bus_width),
430 CTRL_OPTIONS(burst_length),
431 CTRL_OPTIONS(cas_latency_override),
432 CTRL_OPTIONS(cas_latency_override_value),
433 CTRL_OPTIONS(use_derated_caslat),
434 CTRL_OPTIONS(additive_latency_override),
435 CTRL_OPTIONS(additive_latency_override_value),
436 CTRL_OPTIONS(clk_adjust),
437 CTRL_OPTIONS(cpo_override),
438 CTRL_OPTIONS(write_data_delay),
439 CTRL_OPTIONS(half_strength_driver_enable),
440
441 /*
442 * These can probably be changed to 2T_EN and 3T_EN
443 * (using a leading numerical character) without problem
444 */
445 CTRL_OPTIONS(twoT_en),
446 CTRL_OPTIONS(threeT_en),
447 CTRL_OPTIONS(ap_en),
448 CTRL_OPTIONS(bstopre),
449 CTRL_OPTIONS(wrlvl_override),
450 CTRL_OPTIONS(wrlvl_sample),
451 CTRL_OPTIONS(wrlvl_start),
452 CTRL_OPTIONS(rcw_override),
453 CTRL_OPTIONS(rcw_1),
454 CTRL_OPTIONS(rcw_2),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]455 CTRL_OPTIONS(ddr_cdr1),
456 CTRL_OPTIONS(ddr_cdr2),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]457 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
458 CTRL_OPTIONS(tFAW_window_four_activates_ps),
459 CTRL_OPTIONS(trwt_override),
460 CTRL_OPTIONS(trwt),
461 };
462
463 static const unsigned int n_opts = ARRAY_SIZE(options);
464
465 if (handle_option_table(options, n_opts, p,
466 optname_str, value_str))
467 return;
468
469 printf("couldn't find option string %s\n", optname_str);
470}
471
472#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
473 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
474#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
475 offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
476 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
477
478static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
479{
480 unsigned int i;
481 static const struct options_string options[] = {
482 CFG_REGS_CS(0, bnds),
483 CFG_REGS_CS(0, config),
484 CFG_REGS_CS(0, config_2),
485#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
486 CFG_REGS_CS(1, bnds),
487 CFG_REGS_CS(1, config),
488 CFG_REGS_CS(1, config_2),
489#endif
490#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
491 CFG_REGS_CS(2, bnds),
492 CFG_REGS_CS(2, config),
493 CFG_REGS_CS(2, config_2),
494#endif
495#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
496 CFG_REGS_CS(3, bnds),
497 CFG_REGS_CS(3, config),
498 CFG_REGS_CS(3, config_2),
499#endif
500 CFG_REGS(timing_cfg_3),
501 CFG_REGS(timing_cfg_0),
502 CFG_REGS(timing_cfg_1),
503 CFG_REGS(timing_cfg_2),
504 CFG_REGS(ddr_sdram_cfg),
505 CFG_REGS(ddr_sdram_cfg_2),
506 CFG_REGS(ddr_sdram_mode),
507 CFG_REGS(ddr_sdram_mode_2),
508 CFG_REGS(ddr_sdram_mode_3),
509 CFG_REGS(ddr_sdram_mode_4),
510 CFG_REGS(ddr_sdram_mode_5),
511 CFG_REGS(ddr_sdram_mode_6),
512 CFG_REGS(ddr_sdram_mode_7),
513 CFG_REGS(ddr_sdram_mode_8),
514 CFG_REGS(ddr_sdram_interval),
515 CFG_REGS(ddr_data_init),
516 CFG_REGS(ddr_sdram_clk_cntl),
517 CFG_REGS(ddr_init_addr),
518 CFG_REGS(ddr_init_ext_addr),
519 CFG_REGS(timing_cfg_4),
520 CFG_REGS(timing_cfg_5),
521 CFG_REGS(ddr_zq_cntl),
522 CFG_REGS(ddr_wrlvl_cntl),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]523 CFG_REGS(ddr_wrlvl_cntl_2),
524 CFG_REGS(ddr_wrlvl_cntl_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]525 CFG_REGS(ddr_sr_cntr),
526 CFG_REGS(ddr_sdram_rcw_1),
527 CFG_REGS(ddr_sdram_rcw_2),
528 CFG_REGS(ddr_cdr1),
529 CFG_REGS(ddr_cdr2),
530 CFG_REGS(err_disable),
531 CFG_REGS(err_int_en),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]532 CFG_REGS(ddr_eor),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]533 };
534 static const unsigned int n_opts = ARRAY_SIZE(options);
535
536 print_option_table(options, n_opts, ddr);
537
538 for (i = 0; i < 32; i++)
539 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
540}
541
542static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
543 unsigned int ctrl_num,
544 const char *regname,
545 const char *value_str)
546{
547 unsigned int i;
548 fsl_ddr_cfg_regs_t *ddr;
549 char buf[20];
550 static const struct options_string options[] = {
551 CFG_REGS_CS(0, bnds),
552 CFG_REGS_CS(0, config),
553 CFG_REGS_CS(0, config_2),
554#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
555 CFG_REGS_CS(1, bnds),
556 CFG_REGS_CS(1, config),
557 CFG_REGS_CS(1, config_2),
558#endif
559#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
560 CFG_REGS_CS(2, bnds),
561 CFG_REGS_CS(2, config),
562 CFG_REGS_CS(2, config_2),
563#endif
564#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
565 CFG_REGS_CS(3, bnds),
566 CFG_REGS_CS(3, config),
567 CFG_REGS_CS(3, config_2),
568#endif
569 CFG_REGS(timing_cfg_3),
570 CFG_REGS(timing_cfg_0),
571 CFG_REGS(timing_cfg_1),
572 CFG_REGS(timing_cfg_2),
573 CFG_REGS(ddr_sdram_cfg),
574 CFG_REGS(ddr_sdram_cfg_2),
575 CFG_REGS(ddr_sdram_mode),
576 CFG_REGS(ddr_sdram_mode_2),
577 CFG_REGS(ddr_sdram_mode_3),
578 CFG_REGS(ddr_sdram_mode_4),
579 CFG_REGS(ddr_sdram_mode_5),
580 CFG_REGS(ddr_sdram_mode_6),
581 CFG_REGS(ddr_sdram_mode_7),
582 CFG_REGS(ddr_sdram_mode_8),
583 CFG_REGS(ddr_sdram_interval),
584 CFG_REGS(ddr_data_init),
585 CFG_REGS(ddr_sdram_clk_cntl),
586 CFG_REGS(ddr_init_addr),
587 CFG_REGS(ddr_init_ext_addr),
588 CFG_REGS(timing_cfg_4),
589 CFG_REGS(timing_cfg_5),
590 CFG_REGS(ddr_zq_cntl),
591 CFG_REGS(ddr_wrlvl_cntl),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]592 CFG_REGS(ddr_wrlvl_cntl_2),
593 CFG_REGS(ddr_wrlvl_cntl_3),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]594 CFG_REGS(ddr_sr_cntr),
595 CFG_REGS(ddr_sdram_rcw_1),
596 CFG_REGS(ddr_sdram_rcw_2),
597 CFG_REGS(ddr_cdr1),
598 CFG_REGS(ddr_cdr2),
599 CFG_REGS(err_disable),
600 CFG_REGS(err_int_en),
601 CFG_REGS(ddr_sdram_rcw_2),
602 CFG_REGS(ddr_sdram_rcw_2),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]603 CFG_REGS(ddr_eor),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]604 };
605 static const unsigned int n_opts = ARRAY_SIZE(options);
606
607 debug("fsl_ddr_regs_edit: ctrl_num = %u, "
608 "regname = %s, value = %s\n",
609 ctrl_num, regname, value_str);
610 if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
611 return;
612
613 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
614
615 if (handle_option_table(options, n_opts, ddr, regname, value_str))
616 return;
617
618 for (i = 0; i < 32; i++) {
619 unsigned int value = simple_strtoul(value_str, NULL, 0);
620 sprintf(buf, "debug_%u", i + 1);
621 if (strcmp(buf, regname) == 0) {
622 ddr->debug[i] = value;
623 return;
624 }
625 }
626 printf("Error: couldn't find register string %s\n", regname);
627}
628
629#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
630 sizeof((memctl_options_t *)0)->x, 1}
631
632static void print_memctl_options(const memctl_options_t *popts)
633{
634 static const struct options_string options[] = {
635 CTRL_OPTIONS_CS(0, odt_rd_cfg),
636 CTRL_OPTIONS_CS(0, odt_wr_cfg),
637#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
638 CTRL_OPTIONS_CS(1, odt_rd_cfg),
639 CTRL_OPTIONS_CS(1, odt_wr_cfg),
640#endif
641#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
642 CTRL_OPTIONS_CS(2, odt_rd_cfg),
643 CTRL_OPTIONS_CS(2, odt_wr_cfg),
644#endif
645#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
646 CTRL_OPTIONS_CS(3, odt_rd_cfg),
647 CTRL_OPTIONS_CS(3, odt_wr_cfg),
648#endif
649#if defined(CONFIG_FSL_DDR3)
650 CTRL_OPTIONS_CS(0, odt_rtt_norm),
651 CTRL_OPTIONS_CS(0, odt_rtt_wr),
652#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
653 CTRL_OPTIONS_CS(1, odt_rtt_norm),
654 CTRL_OPTIONS_CS(1, odt_rtt_wr),
655#endif
656#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
657 CTRL_OPTIONS_CS(2, odt_rtt_norm),
658 CTRL_OPTIONS_CS(2, odt_rtt_wr),
659#endif
660#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
661 CTRL_OPTIONS_CS(3, odt_rtt_norm),
662 CTRL_OPTIONS_CS(3, odt_rtt_wr),
663#endif
664#endif
665 CTRL_OPTIONS(memctl_interleaving),
666 CTRL_OPTIONS(memctl_interleaving_mode),
667 CTRL_OPTIONS_HEX(ba_intlv_ctl),
668 CTRL_OPTIONS(ECC_mode),
669 CTRL_OPTIONS(ECC_init_using_memctl),
670 CTRL_OPTIONS(DQS_config),
671 CTRL_OPTIONS(self_refresh_in_sleep),
672 CTRL_OPTIONS(dynamic_power),
673 CTRL_OPTIONS(data_bus_width),
674 CTRL_OPTIONS(burst_length),
675 CTRL_OPTIONS(cas_latency_override),
676 CTRL_OPTIONS(cas_latency_override_value),
677 CTRL_OPTIONS(use_derated_caslat),
678 CTRL_OPTIONS(additive_latency_override),
679 CTRL_OPTIONS(additive_latency_override_value),
680 CTRL_OPTIONS(clk_adjust),
681 CTRL_OPTIONS(cpo_override),
682 CTRL_OPTIONS(write_data_delay),
683 CTRL_OPTIONS(half_strength_driver_enable),
684 /*
685 * These can probably be changed to 2T_EN and 3T_EN
686 * (using a leading numerical character) without problem
687 */
688 CTRL_OPTIONS(twoT_en),
689 CTRL_OPTIONS(threeT_en),
690 CTRL_OPTIONS(registered_dimm_en),
691 CTRL_OPTIONS(ap_en),
692 CTRL_OPTIONS(bstopre),
693 CTRL_OPTIONS(wrlvl_override),
694 CTRL_OPTIONS(wrlvl_sample),
695 CTRL_OPTIONS(wrlvl_start),
696 CTRL_OPTIONS(rcw_override),
697 CTRL_OPTIONS(rcw_1),
698 CTRL_OPTIONS(rcw_2),
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]699 CTRL_OPTIONS_HEX(ddr_cdr1),
700 CTRL_OPTIONS_HEX(ddr_cdr2),
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]701 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
702 CTRL_OPTIONS(tFAW_window_four_activates_ps),
703 CTRL_OPTIONS(trwt_override),
704 CTRL_OPTIONS(trwt),
705 };
706 static const unsigned int n_opts = ARRAY_SIZE(options);
707
708 print_option_table(options, n_opts, popts);
709}
710
711#ifdef CONFIG_FSL_DDR1
712void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
713{
714 unsigned int i;
715
716 printf("%-3d : %02x %s\n", 0, spd->info_size,
717 " spd->info_size, * 0 # bytes written into serial memory *");
718 printf("%-3d : %02x %s\n", 1, spd->chip_size,
719 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
720 printf("%-3d : %02x %s\n", 2, spd->mem_type,
721 " spd->mem_type, * 2 Fundamental memory type *");
722 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
723 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
724 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
725 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
726 printf("%-3d : %02x %s\n", 5, spd->nrows,
727 " spd->nrows * 5 # of DIMM Banks *");
728 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb,
729 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *");
730 printf("%-3d : %02x %s\n", 7, spd->dataw_msb,
731 " spd->dataw_msb, * 7 Data Width msb of this assembly *");
732 printf("%-3d : %02x %s\n", 8, spd->voltage,
733 " spd->voltage, * 8 Voltage intf std of this assembly *");
734 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
735 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
736 printf("%-3d : %02x %s\n", 10, spd->clk_access,
737 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
738 printf("%-3d : %02x %s\n", 11, spd->config,
739 " spd->config, * 11 DIMM Configuration type *");
740 printf("%-3d : %02x %s\n", 12, spd->refresh,
741 " spd->refresh, * 12 Refresh Rate/Type *");
742 printf("%-3d : %02x %s\n", 13, spd->primw,
743 " spd->primw, * 13 Primary SDRAM Width *");
744 printf("%-3d : %02x %s\n", 14, spd->ecw,
745 " spd->ecw, * 14 Error Checking SDRAM width *");
746 printf("%-3d : %02x %s\n", 15, spd->min_delay,
747 " spd->min_delay, * 15 Back to Back Random Access *");
748 printf("%-3d : %02x %s\n", 16, spd->burstl,
749 " spd->burstl, * 16 Burst Lengths Supported *");
750 printf("%-3d : %02x %s\n", 17, spd->nbanks,
751 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
752 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
753 " spd->cas_lat, * 18 CAS# Latencies Supported *");
754 printf("%-3d : %02x %s\n", 19, spd->cs_lat,
755 " spd->cs_lat, * 19 Chip Select Latency *");
756 printf("%-3d : %02x %s\n", 20, spd->write_lat,
757 " spd->write_lat, * 20 Write Latency/Recovery *");
758 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
759 " spd->mod_attr, * 21 SDRAM Module Attributes *");
760 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
761 " spd->dev_attr, * 22 SDRAM Device Attributes *");
762 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
763 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
764 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
765 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
766 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
767 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
768 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
769 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
770 printf("%-3d : %02x %s\n", 27, spd->trp,
771 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
772 printf("%-3d : %02x %s\n", 28, spd->trrd,
773 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
774 printf("%-3d : %02x %s\n", 29, spd->trcd,
775 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
776 printf("%-3d : %02x %s\n", 30, spd->tras,
777 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
778 printf("%-3d : %02x %s\n", 31, spd->bank_dens,
779 " spd->bank_dens, * 31 Density of each bank on module *");
780 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
781 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
782 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
783 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
784 printf("%-3d : %02x %s\n", 34, spd->data_setup,
785 " spd->data_setup, * 34 Data signal input setup time *");
786 printf("%-3d : %02x %s\n", 35, spd->data_hold,
787 " spd->data_hold, * 35 Data signal input hold time *");
788 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0],
789 " spd->res_36_40[0], * 36 Reserved / tWR *");
790 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1],
791 " spd->res_36_40[1], * 37 Reserved / tWTR *");
792 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2],
793 " spd->res_36_40[2], * 38 Reserved / tRTP *");
794 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3],
795 " spd->res_36_40[3], * 39 Reserved / mem_probe *");
796 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4],
797 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
798 printf("%-3d : %02x %s\n", 41, spd->trc,
799 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
800 printf("%-3d : %02x %s\n", 42, spd->trfc,
801 " spd->trfc, * 42 Min Auto to Active period tRFC *");
802 printf("%-3d : %02x %s\n", 43, spd->tckmax,
803 " spd->tckmax, * 43 Max device cycle time tCKmax *");
804 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
805 " spd->tdqsq, * 44 Max DQS to DQ skew *");
806 printf("%-3d : %02x %s\n", 45, spd->tqhs,
807 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
808 printf("%-3d : %02x %s\n", 46, spd->res_46,
809 " spd->res_46, * 46 Reserved/ PLL Relock time *");
810 printf("%-3d : %02x %s\n", 47, spd->dimm_height,
811 " spd->dimm_height * 47 SDRAM DIMM Height *");
812
813 printf("%-3d-%3d: ", 48, 61);
814
815 for (i = 0; i < 14; i++)
816 printf("%02x", spd->res_48_61[i]);
817
818 printf(" * 48-61 IDD in SPD and Reserved space *\n");
819
820 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
821 " spd->spd_rev, * 62 SPD Data Revision Code *");
822 printf("%-3d : %02x %s\n", 63, spd->cksum,
823 " spd->cksum, * 63 Checksum for bytes 0-62 *");
824 printf("%-3d-%3d: ", 64, 71);
825
826 for (i = 0; i < 8; i++)
827 printf("%02x", spd->mid[i]);
828
829 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
830 printf("%-3d : %02x %s\n", 72, spd->mloc,
831 " spd->mloc, * 72 Manufacturing Location *");
832
833 printf("%-3d-%3d: >>", 73, 90);
834
835 for (i = 0; i < 18; i++)
836 printf("%c", spd->mpart[i]);
837
838 printf("<<* 73 Manufacturer's Part Number *\n");
839
840 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
841 "* 91 Revision Code *");
842 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
843 "* 93 Manufacturing Date *");
844 printf("%-3d-%3d: ", 95, 98);
845
846 for (i = 0; i < 4; i++)
847 printf("%02x", spd->sernum[i]);
848
849 printf("* 95 Assembly Serial Number *\n");
850
851 printf("%-3d-%3d: ", 99, 127);
852
853 for (i = 0; i < 27; i++)
854 printf("%02x", spd->mspec[i]);
855
856 printf("* 99 Manufacturer Specific Data *\n");
857}
858#endif
859
860#ifdef CONFIG_FSL_DDR2
861void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
862{
863 unsigned int i;
864
865 printf("%-3d : %02x %s\n", 0, spd->info_size,
866 " spd->info_size, * 0 # bytes written into serial memory *");
867 printf("%-3d : %02x %s\n", 1, spd->chip_size,
868 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
869 printf("%-3d : %02x %s\n", 2, spd->mem_type,
870 " spd->mem_type, * 2 Fundamental memory type *");
871 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
872 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
873 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
874 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
875 printf("%-3d : %02x %s\n", 5, spd->mod_ranks,
876 " spd->mod_ranks * 5 # of Module Rows on this assembly *");
877 printf("%-3d : %02x %s\n", 6, spd->dataw,
878 " spd->dataw, * 6 Data Width of this assembly *");
879 printf("%-3d : %02x %s\n", 7, spd->res_7,
880 " spd->res_7, * 7 Reserved *");
881 printf("%-3d : %02x %s\n", 8, spd->voltage,
882 " spd->voltage, * 8 Voltage intf std of this assembly *");
883 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
884 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
885 printf("%-3d : %02x %s\n", 10, spd->clk_access,
886 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
887 printf("%-3d : %02x %s\n", 11, spd->config,
888 " spd->config, * 11 DIMM Configuration type *");
889 printf("%-3d : %02x %s\n", 12, spd->refresh,
890 " spd->refresh, * 12 Refresh Rate/Type *");
891 printf("%-3d : %02x %s\n", 13, spd->primw,
892 " spd->primw, * 13 Primary SDRAM Width *");
893 printf("%-3d : %02x %s\n", 14, spd->ecw,
894 " spd->ecw, * 14 Error Checking SDRAM width *");
895 printf("%-3d : %02x %s\n", 15, spd->res_15,
896 " spd->res_15, * 15 Reserved *");
897 printf("%-3d : %02x %s\n", 16, spd->burstl,
898 " spd->burstl, * 16 Burst Lengths Supported *");
899 printf("%-3d : %02x %s\n", 17, spd->nbanks,
900 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
901 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
902 " spd->cas_lat, * 18 CAS# Latencies Supported *");
903 printf("%-3d : %02x %s\n", 19, spd->mech_char,
904 " spd->mech_char, * 19 Mechanical Characteristics *");
905 printf("%-3d : %02x %s\n", 20, spd->dimm_type,
906 " spd->dimm_type, * 20 DIMM type *");
907 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
908 " spd->mod_attr, * 21 SDRAM Module Attributes *");
909 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
910 " spd->dev_attr, * 22 SDRAM Device Attributes *");
911 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
912 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
913 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
914 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
915 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
916 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
917 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
918 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
919 printf("%-3d : %02x %s\n", 27, spd->trp,
920 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
921 printf("%-3d : %02x %s\n", 28, spd->trrd,
922 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
923 printf("%-3d : %02x %s\n", 29, spd->trcd,
924 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
925 printf("%-3d : %02x %s\n", 30, spd->tras,
926 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
927 printf("%-3d : %02x %s\n", 31, spd->rank_dens,
928 " spd->rank_dens, * 31 Density of each rank on module *");
929 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
930 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
931 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
932 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
933 printf("%-3d : %02x %s\n", 34, spd->data_setup,
934 " spd->data_setup, * 34 Data signal input setup time *");
935 printf("%-3d : %02x %s\n", 35, spd->data_hold,
936 " spd->data_hold, * 35 Data signal input hold time *");
937 printf("%-3d : %02x %s\n", 36, spd->twr,
938 " spd->twr, * 36 Write Recovery time tWR *");
939 printf("%-3d : %02x %s\n", 37, spd->twtr,
940 " spd->twtr, * 37 Int write to read delay tWTR *");
941 printf("%-3d : %02x %s\n", 38, spd->trtp,
942 " spd->trtp, * 38 Int read to precharge delay tRTP *");
943 printf("%-3d : %02x %s\n", 39, spd->mem_probe,
944 " spd->mem_probe, * 39 Mem analysis probe characteristics *");
945 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext,
946 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
947 printf("%-3d : %02x %s\n", 41, spd->trc,
948 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
949 printf("%-3d : %02x %s\n", 42, spd->trfc,
950 " spd->trfc, * 42 Min Auto to Active period tRFC *");
951 printf("%-3d : %02x %s\n", 43, spd->tckmax,
952 " spd->tckmax, * 43 Max device cycle time tCKmax *");
953 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
954 " spd->tdqsq, * 44 Max DQS to DQ skew *");
955 printf("%-3d : %02x %s\n", 45, spd->tqhs,
956 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
957 printf("%-3d : %02x %s\n", 46, spd->pll_relock,
958 " spd->pll_relock, * 46 PLL Relock time *");
959 printf("%-3d : %02x %s\n", 47, spd->Tcasemax,
960 " spd->Tcasemax, * 47 Tcasemax *");
961 printf("%-3d : %02x %s\n", 48, spd->psiTAdram,
962 " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package "
963 "from Top (Case) to Ambient (Psi T-A DRAM) *");
964 printf("%-3d : %02x %s\n", 49, spd->dt0_mode,
965 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from "
966 "Ambient due to Activate-Precharge/Mode Bits "
967 "(DT0/Mode Bits) *)");
968 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q,
969 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from "
970 "Ambient due to Precharge/Quiet Standby "
971 "(DT2N/DT2Q) *");
972 printf("%-3d : %02x %s\n", 51, spd->dt2p,
973 " spd->dt2p, * 51 DRAM Case Temperature Rise from "
974 "Ambient due to Precharge Power-Down (DT2P) *");
975 printf("%-3d : %02x %s\n", 52, spd->dt3n,
976 " spd->dt3n, * 52 DRAM Case Temperature Rise from "
977 "Ambient due to Active Standby (DT3N) *");
978 printf("%-3d : %02x %s\n", 53, spd->dt3pfast,
979 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from "
980 "Ambient due to Active Power-Down with Fast PDN Exit "
981 "(DT3Pfast) *");
982 printf("%-3d : %02x %s\n", 54, spd->dt3pslow,
983 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from "
984 "Ambient due to Active Power-Down with Slow PDN Exit "
985 "(DT3Pslow) *");
986 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w,
987 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
988 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
989 "(DT4R/DT4R4W Mode Bit) *");
990 printf("%-3d : %02x %s\n", 56, spd->dt5b,
991 " spd->dt5b, * 56 DRAM Case Temperature Rise from "
992 "Ambient due to Burst Refresh (DT5B) *");
993 printf("%-3d : %02x %s\n", 57, spd->dt7,
994 " spd->dt7, * 57 DRAM Case Temperature Rise from "
995 "Ambient due to Bank Interleave Reads with "
996 "Auto-Precharge (DT7) *");
997 printf("%-3d : %02x %s\n", 58, spd->psiTApll,
998 " spd->psiTApll, * 58 Thermal Resistance of PLL Package form"
999 " Top (Case) to Ambient (Psi T-A PLL) *");
1000 printf("%-3d : %02x %s\n", 59, spd->psiTAreg,
1001 " spd->psiTAreg, * 59 Thermal Reisitance of Register Package"
1002 " from Top (Case) to Ambient (Psi T-A Register) *");
1003 printf("%-3d : %02x %s\n", 60, spd->dtpllactive,
1004 " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1005 "Ambient due to PLL Active (DT PLL Active) *");
1006 printf("%-3d : %02x %s\n", 61, spd->dtregact,
1007 " spd->dtregact, "
1008 "* 61 Register Case Temperature Rise from Ambient due to "
1009 "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1010 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
1011 " spd->spd_rev, * 62 SPD Data Revision Code *");
1012 printf("%-3d : %02x %s\n", 63, spd->cksum,
1013 " spd->cksum, * 63 Checksum for bytes 0-62 *");
1014
1015 printf("%-3d-%3d: ", 64, 71);
1016
1017 for (i = 0; i < 8; i++)
1018 printf("%02x", spd->mid[i]);
1019
1020 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1021
1022 printf("%-3d : %02x %s\n", 72, spd->mloc,
1023 " spd->mloc, * 72 Manufacturing Location *");
1024
1025 printf("%-3d-%3d: >>", 73, 90);
1026 for (i = 0; i < 18; i++)
1027 printf("%c", spd->mpart[i]);
1028
1029
1030 printf("<<* 73 Manufacturer's Part Number *\n");
1031
1032 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1033 "* 91 Revision Code *");
1034 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1035 "* 93 Manufacturing Date *");
1036 printf("%-3d-%3d: ", 95, 98);
1037
1038 for (i = 0; i < 4; i++)
1039 printf("%02x", spd->sernum[i]);
1040
1041 printf("* 95 Assembly Serial Number *\n");
1042
1043 printf("%-3d-%3d: ", 99, 127);
1044 for (i = 0; i < 27; i++)
1045 printf("%02x", spd->mspec[i]);
1046
1047
1048 printf("* 99 Manufacturer Specific Data *\n");
1049}
1050#endif
1051
1052#ifdef CONFIG_FSL_DDR3
1053void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1054{
1055 unsigned int i;
1056
1057 /* General Section: Bytes 0-59 */
1058
York Sun1d083ff2012-08-17 08:22:43 +0000[diff] [blame]1059#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1060#define PRINT_NNXXS(n0, n1, x0, x1, s) \
1061 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1062
1063 PRINT_NXS(0, spd->info_size_crc,
1064 "info_size_crc bytes written into serial memory, "
1065 "CRC coverage");
1066 PRINT_NXS(1, spd->spd_rev,
1067 "spd_rev SPD Revision");
1068 PRINT_NXS(2, spd->mem_type,
1069 "mem_type Key Byte / DRAM Device Type");
1070 PRINT_NXS(3, spd->module_type,
1071 "module_type Key Byte / Module Type");
1072 PRINT_NXS(4, spd->density_banks,
1073 "density_banks SDRAM Density and Banks");
1074 PRINT_NXS(5, spd->addressing,
1075 "addressing SDRAM Addressing");
1076 PRINT_NXS(6, spd->module_vdd,
1077 "module_vdd Module Nominal Voltage, VDD");
1078 PRINT_NXS(7, spd->organization,
1079 "organization Module Organization");
1080 PRINT_NXS(8, spd->bus_width,
1081 "bus_width Module Memory Bus Width");
1082 PRINT_NXS(9, spd->ftb_div,
1083 "ftb_div Fine Timebase (FTB) Dividend / Divisor");
1084 PRINT_NXS(10, spd->mtb_dividend,
1085 "mtb_dividend Medium Timebase (MTB) Dividend");
1086 PRINT_NXS(11, spd->mtb_divisor,
1087 "mtb_divisor Medium Timebase (MTB) Divisor");
1088 PRINT_NXS(12, spd->tCK_min,
1089 "tCK_min SDRAM Minimum Cycle Time");
1090 PRINT_NXS(13, spd->res_13,
1091 "res_13 Reserved");
1092 PRINT_NXS(14, spd->caslat_lsb,
1093 "caslat_lsb CAS Latencies Supported, LSB");
1094 PRINT_NXS(15, spd->caslat_msb,
1095 "caslat_msb CAS Latencies Supported, MSB");
1096 PRINT_NXS(16, spd->tAA_min,
1097 "tAA_min Min CAS Latency Time");
1098 PRINT_NXS(17, spd->tWR_min,
1099 "tWR_min Min Write REcovery Time");
1100 PRINT_NXS(18, spd->tRCD_min,
1101 "tRCD_min Min RAS# to CAS# Delay Time");
1102 PRINT_NXS(19, spd->tRRD_min,
1103 "tRRD_min Min Row Active to Row Active Delay Time");
1104 PRINT_NXS(20, spd->tRP_min,
1105 "tRP_min Min Row Precharge Delay Time");
1106 PRINT_NXS(21, spd->tRAS_tRC_ext,
1107 "tRAS_tRC_ext Upper Nibbles for tRAS and tRC");
1108 PRINT_NXS(22, spd->tRAS_min_lsb,
1109 "tRAS_min_lsb Min Active to Precharge Delay Time, LSB");
1110 PRINT_NXS(23, spd->tRC_min_lsb,
1111 "tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1112 PRINT_NXS(24, spd->tRFC_min_lsb,
1113 "tRFC_min_lsb Min Refresh Recovery Delay Time LSB");
1114 PRINT_NXS(25, spd->tRFC_min_msb,
1115 "tRFC_min_msb Min Refresh Recovery Delay Time MSB");
1116 PRINT_NXS(26, spd->tWTR_min,
1117 "tWTR_min Min Internal Write to Read Command Delay Time");
1118 PRINT_NXS(27, spd->tRTP_min,
1119 "tRTP_min "
1120 "Min Internal Read to Precharge Command Delay Time");
1121 PRINT_NXS(28, spd->tFAW_msb,
1122 "tFAW_msb Upper Nibble for tFAW");
1123 PRINT_NXS(29, spd->tFAW_min,
1124 "tFAW_min Min Four Activate Window Delay Time");
1125 PRINT_NXS(30, spd->opt_features,
1126 "opt_features SDRAM Optional Features");
1127 PRINT_NXS(31, spd->therm_ref_opt,
1128 "therm_ref_opt SDRAM Thermal and Refresh Opts");
1129 PRINT_NXS(32, spd->therm_sensor,
1130 "therm_sensor SDRAM Thermal Sensor");
1131 PRINT_NXS(33, spd->device_type,
1132 "device_type SDRAM Device Type");
York Sun73b53962012-08-17 08:22:37 +0000[diff] [blame]1133 PRINT_NXS(34, spd->fine_tCK_min,
1134 "fine_tCK_min Fine offset for tCKmin");
1135 PRINT_NXS(35, spd->fine_tAA_min,
1136 "fine_tAA_min Fine offset for tAAmin");
1137 PRINT_NXS(36, spd->fine_tRCD_min,
1138 "fine_tRCD_min Fine offset for tRCDmin");
1139 PRINT_NXS(37, spd->fine_tRP_min,
1140 "fine_tRP_min Fine offset for tRPmin");
1141 PRINT_NXS(38, spd->fine_tRC_min,
1142 "fine_tRC_min Fine offset for tRCmin");
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1143
York Sun73b53962012-08-17 08:22:37 +0000[diff] [blame]1144 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1145
York Sun73b53962012-08-17 08:22:37 +0000[diff] [blame]1146 for (i = 39; i <= 59; i++)
1147 printf("%02x ", spd->res_39_59[i - 39]);
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1148
1149 puts("\n");
1150
1151 switch (spd->module_type) {
1152 case 0x02: /* UDIMM */
1153 case 0x03: /* SO-DIMM */
1154 case 0x04: /* Micro-DIMM */
1155 case 0x06: /* Mini-UDIMM */
1156 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1157 "mod_height (Unbuffered) Module Nominal Height");
1158 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1159 "mod_thickness (Unbuffered) Module Maximum Thickness");
1160 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1161 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1162 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1163 "addr_mapping (Unbuffered) Address mapping from "
1164 "Edge Connector to DRAM");
1165 break;
1166 case 0x01: /* RDIMM */
1167 case 0x05: /* Mini-RDIMM */
1168 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1169 "mod_height (Registered) Module Nominal Height");
1170 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1171 "mod_thickness (Registered) Module Maximum Thickness");
1172 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1173 "ref_raw_card (Registered) Reference Raw Card Used");
1174 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1175 "modu_attr (Registered) DIMM Module Attributes");
1176 PRINT_NXS(64, spd->mod_section.registered.thermal,
1177 "thermal (Registered) Thermal Heat "
1178 "Spreader Solution");
1179 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1180 "reg_id_lo (Registered) Register Manufacturer ID "
1181 "Code, LSB");
1182 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1183 "reg_id_hi (Registered) Register Manufacturer ID "
1184 "Code, MSB");
1185 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1186 "reg_rev (Registered) Register "
1187 "Revision Number");
1188 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1189 "reg_type (Registered) Register Type");
1190 for (i = 69; i <= 76; i++) {
1191 printf("%-3d : %02x rcw[%d]\n", i,
1192 spd->mod_section.registered.rcw[i-69], i-69);
1193 }
1194 break;
1195 default:
1196 /* Module-specific Section, Unsupported Module Type */
1197 printf("%-3d-%3d: ", 60, 116);
1198
1199 for (i = 60; i <= 116; i++)
1200 printf("%02x", spd->mod_section.uc[i - 60]);
1201
1202 break;
1203 }
1204
1205 /* Unique Module ID: Bytes 117-125 */
1206 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1207 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1208 PRINT_NXS(119, spd->mloc, "Mfg Location");
1209 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1210
1211 printf("%-3d-%3d: ", 122, 125);
1212
1213 for (i = 122; i <= 125; i++)
1214 printf("%02x ", spd->sernum[i - 122]);
1215 printf(" Module Serial Number\n");
1216
1217 /* CRC: Bytes 126-127 */
1218 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1219
1220 /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1221 printf("%-3d-%3d: ", 128, 145);
1222 for (i = 128; i <= 145; i++)
1223 printf("%02x ", spd->mpart[i - 128]);
1224 printf(" Mfg's Module Part Number\n");
1225
1226 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1227 "Module Revision code");
1228
1229 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1230 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1231
1232 printf("%-3d-%3d: ", 150, 175);
1233 for (i = 150; i <= 175; i++)
1234 printf("%02x ", spd->msd[i - 150]);
1235 printf(" Mfg's Specific Data\n");
1236
1237 printf("%-3d-%3d: ", 176, 255);
1238 for (i = 176; i <= 255; i++)
1239 printf("%02x", spd->cust[i - 176]);
1240 printf(" Mfg's Specific Data\n");
1241
1242}
1243#endif
1244
1245static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1246{
1247#if defined(CONFIG_FSL_DDR1)
1248 ddr1_spd_dump(spd);
1249#elif defined(CONFIG_FSL_DDR2)
1250 ddr2_spd_dump(spd);
1251#elif defined(CONFIG_FSL_DDR3)
1252 ddr3_spd_dump(spd);
1253#endif
1254}
1255
1256static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1257 unsigned int ctrl_mask,
1258 unsigned int dimm_mask,
1259 unsigned int do_mask)
1260{
1261 unsigned int i, j, retval;
1262
1263 /* STEP 1: DIMM SPD data */
1264 if (do_mask & STEP_GET_SPD) {
1265 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1266 if (!(ctrl_mask & (1 << i)))
1267 continue;
1268
1269 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1270 if (!(dimm_mask & (1 << j)))
1271 continue;
1272
1273 printf("SPD info: Controller=%u "
1274 "DIMM=%u\n", i, j);
1275 generic_spd_dump(
1276 &(pinfo->spd_installed_dimms[i][j]));
1277 printf("\n");
1278 }
1279 printf("\n");
1280 }
1281 printf("\n");
1282 }
1283
1284 /* STEP 2: DIMM Parameters */
1285 if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1286 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1287 if (!(ctrl_mask & (1 << i)))
1288 continue;
1289 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1290 if (!(dimm_mask & (1 << j)))
1291 continue;
1292 printf("DIMM parameters: Controller=%u "
1293 "DIMM=%u\n", i, j);
1294 print_dimm_parameters(
1295 &(pinfo->dimm_params[i][j]));
1296 printf("\n");
1297 }
1298 printf("\n");
1299 }
1300 printf("\n");
1301 }
1302
1303 /* STEP 3: Common Parameters */
1304 if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1305 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1306 if (!(ctrl_mask & (1 << i)))
1307 continue;
1308 printf("\"lowest common\" DIMM parameters: "
1309 "Controller=%u\n", i);
1310 print_lowest_common_dimm_parameters(
1311 &pinfo->common_timing_params[i]);
1312 printf("\n");
1313 }
1314 printf("\n");
1315 }
1316
1317 /* STEP 4: User Configuration Options */
1318 if (do_mask & STEP_GATHER_OPTS) {
1319 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1320 if (!(ctrl_mask & (1 << i)))
1321 continue;
1322 printf("User Config Options: Controller=%u\n", i);
1323 print_memctl_options(&pinfo->memctl_opts[i]);
1324 printf("\n");
1325 }
1326 printf("\n");
1327 }
1328
1329 /* STEP 5: Address assignment */
1330 if (do_mask & STEP_ASSIGN_ADDRESSES) {
1331 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1332 if (!(ctrl_mask & (1 << i)))
1333 continue;
1334 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1335 printf("Address Assignment: Controller=%u "
1336 "DIMM=%u\n", i, j);
1337 printf("Don't have this functionality yet\n");
1338 }
1339 printf("\n");
1340 }
1341 printf("\n");
1342 }
1343
1344 /* STEP 6: computed controller register values */
1345 if (do_mask & STEP_COMPUTE_REGS) {
1346 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1347 if (!(ctrl_mask & (1 << i)))
1348 continue;
1349 printf("Computed Register Values: Controller=%u\n", i);
1350 print_fsl_memctl_config_regs(
1351 &pinfo->fsl_ddr_config_reg[i]);
1352 retval = check_fsl_memctl_config_regs(
1353 &pinfo->fsl_ddr_config_reg[i]);
1354 if (retval) {
1355 printf("check_fsl_memctl_config_regs "
1356 "result = %u\n", retval);
1357 }
1358 printf("\n");
1359 }
1360 printf("\n");
1361 }
1362}
1363
1364struct data_strings {
1365 const char *data_name;
1366 unsigned int step_mask;
1367 unsigned int dimm_number_required;
1368};
1369
1370#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1371
1372unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
1373{
1374 unsigned long long ddrsize;
1375 const char *prompt = "FSL DDR>";
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1376 char buffer[CONFIG_SYS_CBSIZE];
1377 char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
1378 int argc;
1379 unsigned int next_step = STEP_GET_SPD;
1380 static const struct data_strings options[] = {
1381 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1382 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1383 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1384 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1385 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1386 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1387 };
1388 static const unsigned int n_opts = ARRAY_SIZE(options);
1389 const char *usage = {
1390 "commands:\n"
1391 "print print SPD and intermediate computed data\n"
1392 "reset reboot machine\n"
1393 "recompute reload SPD and options to default and recompute regs\n"
1394 "edit modify spd, parameter, or option\n"
1395 "compute recompute registers from current next_step to end\n"
1396 "next_step shows current next_step\n"
1397 "help this message\n"
1398 "go program the memory controller and continue with u-boot\n"
1399 };
1400
1401 /*
1402 * The strategy for next_step is that it points to the next
1403 * step in the computation process that needs to be done.
1404 */
1405 while (1) {
1406 /*
1407 * No need to worry for buffer overflow here in
1408 * this function; readline() maxes out at CFG_CBSIZE
1409 */
York Sun1d083ff2012-08-17 08:22:43 +0000[diff] [blame]1410 readline_into_buffer(prompt, buffer, 0);
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1411 argc = parse_line(buffer, argv);
1412 if (argc == 0)
1413 continue;
1414
1415
1416 if (strcmp(argv[0], "help") == 0) {
1417 puts(usage);
1418 continue;
1419 }
1420
1421 if (strcmp(argv[0], "next_step") == 0) {
1422 printf("next_step = 0x%02X (%s)\n",
1423 next_step,
1424 step_to_string(next_step));
1425 continue;
1426 }
1427
1428 if (strcmp(argv[0], "edit") == 0) {
1429 unsigned int i, j;
1430 unsigned int error = 0;
1431 unsigned int step_mask = 0;
1432 unsigned int ctlr_mask = 0;
1433 unsigned int dimm_mask = 0;
1434 char *p_element = NULL;
1435 char *p_value = NULL;
1436 unsigned int dimm_number_required = 0;
1437 unsigned int ctrl_num;
1438 unsigned int dimm_num;
1439 unsigned int matched = 0;
1440
1441 if (argc == 1) {
1442 /* Only the element and value must be last */
1443 printf("edit <c#> <d#> "
1444 "<spd|dimmparms|commonparms|opts|"
1445 "addresses|regs> <element> <value>\n");
1446 printf("for spd, specify byte number for "
1447 "element\n");
1448 continue;
1449 }
1450
1451 for (i = 1; i < argc - 2; i++) {
1452 for (j = 0; j < n_opts; j++) {
1453 if (strcmp(options[j].data_name,
1454 argv[i]) != 0)
1455 continue;
1456 step_mask |= options[j].step_mask;
1457 dimm_number_required =
1458 options[j].dimm_number_required;
1459 matched = 1;
1460 break;
1461 }
1462
1463 if (matched)
1464 continue;
1465
1466 if (argv[i][0] == 'c') {
1467 char c = argv[i][1];
1468 if (isdigit(c))
1469 ctlr_mask |= 1 << (c - '0');
1470 continue;
1471 }
1472
1473 if (argv[i][0] == 'd') {
1474 char c = argv[i][1];
1475 if (isdigit(c))
1476 dimm_mask |= 1 << (c - '0');
1477 continue;
1478 }
1479
1480 printf("unknown arg %s\n", argv[i]);
1481 step_mask = 0;
1482 error = 1;
1483 break;
1484 }
1485
1486
1487 if (error)
1488 continue;
1489
1490
1491 /* Check arguments */
1492
1493 /* ERROR: If no steps were found */
1494 if (step_mask == 0) {
1495 printf("Error: No valid steps were specified "
1496 "in argument.\n");
1497 continue;
1498 }
1499
1500 /* ERROR: If multiple steps were found */
1501 if (step_mask & (step_mask - 1)) {
1502 printf("Error: Multiple steps specified in "
1503 "argument.\n");
1504 continue;
1505 }
1506
1507 /* ERROR: Controller not specified */
1508 if (ctlr_mask == 0) {
1509 printf("Error: controller number not "
1510 "specified or no element and "
1511 "value specified\n");
1512 continue;
1513 }
1514
1515 if (ctlr_mask & (ctlr_mask - 1)) {
1516 printf("Error: multiple controllers "
1517 "specified, %X\n", ctlr_mask);
1518 continue;
1519 }
1520
1521 /* ERROR: DIMM number not specified */
1522 if (dimm_number_required && dimm_mask == 0) {
1523 printf("Error: DIMM number number not "
1524 "specified or no element and "
1525 "value specified\n");
1526 continue;
1527 }
1528
1529 if (dimm_mask & (dimm_mask - 1)) {
1530 printf("Error: multipled DIMMs specified\n");
1531 continue;
1532 }
1533
1534 p_element = argv[argc - 2];
1535 p_value = argv[argc - 1];
1536
1537 ctrl_num = __ilog2(ctlr_mask);
1538 dimm_num = __ilog2(dimm_mask);
1539
1540 switch (step_mask) {
1541 case STEP_GET_SPD:
1542 {
1543 unsigned int element_num;
1544 unsigned int value;
1545
1546 element_num = simple_strtoul(p_element,
1547 NULL, 0);
1548 value = simple_strtoul(p_value,
1549 NULL, 0);
1550 fsl_ddr_spd_edit(pinfo,
1551 ctrl_num,
1552 dimm_num,
1553 element_num,
1554 value);
1555 next_step = STEP_COMPUTE_DIMM_PARMS;
1556 }
1557 break;
1558
1559 case STEP_COMPUTE_DIMM_PARMS:
1560 fsl_ddr_dimm_parameters_edit(
1561 pinfo, ctrl_num, dimm_num,
1562 p_element, p_value);
1563 next_step = STEP_COMPUTE_COMMON_PARMS;
1564 break;
1565
1566 case STEP_COMPUTE_COMMON_PARMS:
1567 lowest_common_dimm_parameters_edit(pinfo,
1568 ctrl_num, p_element, p_value);
1569 next_step = STEP_GATHER_OPTS;
1570 break;
1571
1572 case STEP_GATHER_OPTS:
1573 fsl_ddr_options_edit(pinfo, ctrl_num,
1574 p_element, p_value);
1575 next_step = STEP_ASSIGN_ADDRESSES;
1576 break;
1577
1578 case STEP_ASSIGN_ADDRESSES:
1579 printf("editing of address assignment "
1580 "not yet implemented\n");
1581 break;
1582
1583 case STEP_COMPUTE_REGS:
1584 {
1585 fsl_ddr_regs_edit(pinfo,
1586 ctrl_num,
1587 p_element,
1588 p_value);
1589 next_step = STEP_PROGRAM_REGS;
1590 }
1591 break;
1592
1593 default:
1594 printf("programming error\n");
1595 while (1)
1596 ;
1597 break;
1598 }
1599 continue;
1600 }
1601
1602 if (strcmp(argv[0], "reset") == 0) {
1603 /*
1604 * Reboot machine.
1605 * Args don't seem to matter because this
1606 * doesn't return
1607 */
1608 do_reset(NULL, 0, 0, NULL);
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]1609 printf("Reset didn't work\n");
York Sun6f5e1dc2011-09-16 13:21:35 -0700[diff] [blame]1610 }
1611
1612 if (strcmp(argv[0], "recompute") == 0) {
1613 /*
1614 * Recalculate everything, starting with
1615 * loading SPD EEPROM from DIMMs
1616 */
1617 next_step = STEP_GET_SPD;
1618 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1619 continue;
1620 }
1621
1622 if (strcmp(argv[0], "compute") == 0) {
1623 /*
1624 * Compute rest of steps starting at
1625 * the current next_step/
1626 */
1627 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1628 continue;
1629 }
1630
1631 if (strcmp(argv[0], "print") == 0) {
1632 unsigned int i, j;
1633 unsigned int error = 0;
1634 unsigned int step_mask = 0;
1635 unsigned int ctlr_mask = 0;
1636 unsigned int dimm_mask = 0;
1637 unsigned int matched = 0;
1638
1639 if (argc == 1) {
1640 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
1641 "[commonparms] [opts] [addresses] [regs]\n");
1642 continue;
1643 }
1644
1645 for (i = 1; i < argc; i++) {
1646 for (j = 0; j < n_opts; j++) {
1647 if (strcmp(options[j].data_name,
1648 argv[i]) != 0)
1649 continue;
1650 step_mask |= options[j].step_mask;
1651 matched = 1;
1652 break;
1653 }
1654
1655 if (matched)
1656 continue;
1657
1658 if (argv[i][0] == 'c') {
1659 char c = argv[i][1];
1660 if (isdigit(c))
1661 ctlr_mask |= 1 << (c - '0');
1662 continue;
1663 }
1664
1665 if (argv[i][0] == 'd') {
1666 char c = argv[i][1];
1667 if (isdigit(c))
1668 dimm_mask |= 1 << (c - '0');
1669 continue;
1670 }
1671
1672 printf("unknown arg %s\n", argv[i]);
1673 step_mask = 0;
1674 error = 1;
1675 break;
1676 }
1677
1678 if (error)
1679 continue;
1680
1681 /* If no particular controller was found, print all */
1682 if (ctlr_mask == 0)
1683 ctlr_mask = 0xFF;
1684
1685 /* If no particular dimm was found, print all dimms. */
1686 if (dimm_mask == 0)
1687 dimm_mask = 0xFF;
1688
1689 /* If no steps were found, print all steps. */
1690 if (step_mask == 0)
1691 step_mask = STEP_ALL;
1692
1693 fsl_ddr_printinfo(pinfo, ctlr_mask,
1694 dimm_mask, step_mask);
1695 continue;
1696 }
1697
1698 if (strcmp(argv[0], "go") == 0) {
1699 if (next_step)
1700 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1701 break;
1702 }
1703
1704 printf("unknown command %s\n", argv[0]);
1705 }
1706
1707 debug("end of memory = %llu\n", (u64)ddrsize);
1708
1709 return ddrsize;
1710}