blob: b20fb1c0a282c5499f6a8d580991a6acb7a943f6 [file] [log] [blame]
Matthias Fuchs15a08bc2008-01-17 10:52:30 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_ARCH(powerpc)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010025/* Do we need any of these for elf?
26 __DYNAMIC = 0; */
27SECTIONS
28{
29 .resetvec 0xFFFFFFFC :
30 {
31 *(.resetvec)
32 } = 0xffff
33
34 .bootpg 0xFFFFF000 :
35 {
36 cpu/ppc4xx/start.o (.bootpg)
37 } = 0xffff
38
39 /* Read-only sections, merged into text segment: */
40 . = + SIZEOF_HEADERS;
41 .interp : { *(.interp) }
42 .hash : { *(.hash) }
43 .dynsym : { *(.dynsym) }
44 .dynstr : { *(.dynstr) }
45 .rel.text : { *(.rel.text) }
Wolfgang Denk53677ef2008-05-20 16:00:29 +020046 .rela.text : { *(.rela.text) }
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010047 .rel.data : { *(.rel.data) }
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048 .rela.data : { *(.rela.data) }
49 .rel.rodata : { *(.rel.rodata) }
50 .rela.rodata : { *(.rela.rodata) }
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010051 .rel.got : { *(.rel.got) }
52 .rela.got : { *(.rela.got) }
53 .rel.ctors : { *(.rel.ctors) }
54 .rela.ctors : { *(.rela.ctors) }
55 .rel.dtors : { *(.rel.dtors) }
56 .rela.dtors : { *(.rela.dtors) }
57 .rel.bss : { *(.rel.bss) }
58 .rela.bss : { *(.rela.bss) }
59 .rel.plt : { *(.rel.plt) }
60 .rela.plt : { *(.rela.plt) }
61 .init : { *(.init) }
62 .plt : { *(.plt) }
63 .text :
64 {
65 /* WARNING - the following is hand-optimized to fit within */
66 /* the sector layout of our flash chips! XXX FIXME XXX */
67
68 cpu/ppc4xx/start.o (.text)
69
70 *(.text)
71 *(.fixup)
72 *(.got1)
73 }
74 _etext = .;
75 PROVIDE (etext = .);
76 .rodata :
77 {
78 *(.rodata)
79 *(.rodata1)
80 *(.rodata.str1.4)
81 }
82 .fini : { *(.fini) } =0
83 .ctors : { *(.ctors) }
84 .dtors : { *(.dtors) }
85
86 /* Read-write section, merged into data segment: */
87 . = (. + 0x00FF) & 0xFFFFFF00;
88 _erotext = .;
89 PROVIDE (erotext = .);
90 .reloc :
91 {
92 *(.got)
93 _GOT2_TABLE_ = .;
94 *(.got2)
95 _FIXUP_TABLE_ = .;
96 *(.fixup)
97 }
98 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
99 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
100
101 .data :
102 {
103 *(.data)
104 *(.data1)
105 *(.sdata)
106 *(.sdata2)
107 *(.dynamic)
108 CONSTRUCTORS
109 }
110 _edata = .;
111 PROVIDE (edata = .);
112
113 . = .;
114 __u_boot_cmd_start = .;
115 .u_boot_cmd : { *(.u_boot_cmd) }
116 __u_boot_cmd_end = .;
117
118
119 . = .;
120 __start___ex_table = .;
121 __ex_table : { *(__ex_table) }
122 __stop___ex_table = .;
123
124 . = ALIGN(256);
125 __init_begin = .;
126 .text.init : { *(.text.init) }
127 .data.init : { *(.data.init) }
128 . = ALIGN(256);
129 __init_end = .;
130
131 __bss_start = .;
132 .bss (NOLOAD) :
133 {
134 *(.sbss) *(.scommon)
135 *(.dynbss)
136 *(.bss)
137 *(COMMON)
138 }
139
140 ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
141
142 _end = . ;
143 PROVIDE (end = .);
144}