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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
Stefan Roesedbbd1252007-10-05 17:10:59 +02002 * (C) Copyright 2000-2007
wdenk4a9cbbe2002-08-27 09:48:53 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00006 */
7
8#include <common.h>
9#include <watchdog.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020010#include <asm/ppc4xx-emac.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000011#include <asm/processor.h>
Stefan Roese09887762010-09-16 14:30:37 +020012#include <asm/ppc4xx-gpio.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020013#include <asm/ppc4xx.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000014
Wolfgang Denkd87080b2006-03-31 18:32:53 +020015DECLARE_GLOBAL_DATA_PTR;
Wolfgang Denkd87080b2006-03-31 18:32:53 +020016
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020017#ifndef CONFIG_SYS_PLL_RECONFIG
18#define CONFIG_SYS_PLL_RECONFIG 0
Mike Nussf66e2c82008-02-20 11:54:20 -050019#endif
20
Stefan Roesefe7cca72010-05-19 11:13:24 +020021#if defined(CONFIG_440EPX) || \
22 defined(CONFIG_460EX) || defined(CONFIG_460GT)
23static void reset_with_rli(void)
24{
25 u32 reg;
26
27 /*
28 * Set reload inhibit so configuration will persist across
29 * processor resets
30 */
31 mfcpr(CPR0_ICFG, reg);
32 reg |= CPR0_ICFG_RLI_MASK;
33 mtcpr(CPR0_ICFG, reg);
34
35 /* Reset processor if configuration changed */
36 __asm__ __volatile__ ("sync; isync");
37 mtspr(SPRN_DBCR0, 0x20000000);
38}
39#endif
40
Mike Nussf66e2c82008-02-20 11:54:20 -050041void reconfigure_pll(u32 new_cpu_freq)
42{
43#if defined(CONFIG_440EPX)
44 int reset_needed = 0;
45 u32 reg, temp;
46 u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
47 fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
48 fbdv, target_fbdv, lfbdv, target_lfbdv,
49 perdv0, target_perdv0, /* CLK_PERD */
50 spcid0, target_spcid0; /* CLK_SPCID */
51
52 /* Reconfigure clocks if necessary.
53 * See PPC440EPx User's Manual, sections 8.2 and 14 */
54 if (new_cpu_freq == 667) {
55 target_prbdv0 = 2;
56 target_fwdva = 2;
57 target_fwdvb = 4;
58 target_fbdv = 20;
59 target_lfbdv = 1;
60 target_perdv0 = 4;
61 target_spcid0 = 4;
62
Niklaus Gigerddc922f2009-10-04 20:04:20 +020063 mfcpr(CPR0_PRIMBD0, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -050064 temp = (reg & PRBDV_MASK) >> 24;
65 prbdv0 = temp ? temp : 8;
66 if (prbdv0 != target_prbdv0) {
67 reg &= ~PRBDV_MASK;
68 reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
Niklaus Gigerddc922f2009-10-04 20:04:20 +020069 mtcpr(CPR0_PRIMBD0, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -050070 reset_needed = 1;
71 }
72
Stefan Roesed1c3b272009-09-09 16:25:29 +020073 mfcpr(CPR0_PLLD, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -050074
75 temp = (reg & PLLD_FWDVA_MASK) >> 16;
76 fwdva = temp ? temp : 16;
77
78 temp = (reg & PLLD_FWDVB_MASK) >> 8;
79 fwdvb = temp ? temp : 8;
80
81 temp = (reg & PLLD_FBDV_MASK) >> 24;
82 fbdv = temp ? temp : 32;
83
84 temp = (reg & PLLD_LFBDV_MASK);
85 lfbdv = temp ? temp : 64;
86
87 if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
88 reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
89 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
90 reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
91 ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
92 ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
93 (target_lfbdv == 64 ? 0 : target_lfbdv);
Stefan Roesed1c3b272009-09-09 16:25:29 +020094 mtcpr(CPR0_PLLD, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -050095 reset_needed = 1;
96 }
97
Stefan Roesed1c3b272009-09-09 16:25:29 +020098 mfcpr(CPR0_PERD, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -050099 perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
100 if (perdv0 != target_perdv0) {
101 reg &= ~CPR0_PERD_PERDV0_MASK;
102 reg |= (target_perdv0 << 24);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200103 mtcpr(CPR0_PERD, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -0500104 reset_needed = 1;
105 }
106
Stefan Roesed1c3b272009-09-09 16:25:29 +0200107 mfcpr(CPR0_SPCID, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -0500108 temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
109 spcid0 = temp ? temp : 4;
110 if (spcid0 != target_spcid0) {
111 reg &= ~CPR0_SPCID_SPCIDV0_MASK;
112 reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200113 mtcpr(CPR0_SPCID, reg);
Mike Nussf66e2c82008-02-20 11:54:20 -0500114 reset_needed = 1;
115 }
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530116 }
Mike Nussf66e2c82008-02-20 11:54:20 -0500117
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530118 /* Get current value of FWDVA.*/
119 mfcpr(CPR0_PLLD, reg);
120 temp = (reg & PLLD_FWDVA_MASK) >> 16;
121
122 /*
123 * Check to see if FWDVA has been set to value of 1. if it has we must
124 * modify it.
125 */
126 if (temp == 1) {
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530127 /*
128 * Load register that contains current boot strapping option.
129 */
130 mfcpr(CPR0_ICFG, reg);
Stefan Roesec1ab75c2010-08-26 17:14:51 +0200131 /*
132 * Strapping option bits (ICS) are already in correct position,
133 * only masking needed.
134 */
135 reg &= CPR0_ICFG_ICS_MASK;
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530136
137 if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
138 (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
Stefan Roesec1ab75c2010-08-26 17:14:51 +0200139 mfcpr(CPR0_PLLD, reg);
140
141 /* Get current value of fbdv. */
142 temp = (reg & PLLD_FBDV_MASK) >> 24;
143 fbdv = temp ? temp : 32;
144
145 /* Get current value of lfbdv. */
146 temp = (reg & PLLD_LFBDV_MASK);
147 lfbdv = temp ? temp : 64;
148
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530149 /*
150 * Get current value of FWDVA. Assign current FWDVA to
151 * new FWDVB.
152 */
153 mfcpr(CPR0_PLLD, reg);
154 target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
155 fwdvb = target_fwdvb ? target_fwdvb : 8;
Stefan Roesec1ab75c2010-08-26 17:14:51 +0200156
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530157 /*
158 * Get current value of FWDVB. Assign current FWDVB to
159 * new FWDVA.
160 */
161 target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
162 fwdva = target_fwdva ? target_fwdva : 16;
Stefan Roesec1ab75c2010-08-26 17:14:51 +0200163
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530164 /*
165 * Update CPR0_PLLD with switched FWDVA and FWDVB.
166 */
167 reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
168 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
169 reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
170 ((fwdvb == 8 ? 0 : fwdvb) << 8) |
171 ((fbdv == 32 ? 0 : fbdv) << 24) |
172 (lfbdv == 64 ? 0 : lfbdv);
173 mtcpr(CPR0_PLLD, reg);
Stefan Roesec1ab75c2010-08-26 17:14:51 +0200174
Rupjyoti Sarmahc550afa2010-03-24 16:52:02 +0530175 /* Acknowledge that a reset is required. */
176 reset_needed = 1;
177 }
178 }
179
Stefan Roesefe7cca72010-05-19 11:13:24 +0200180 /* Now reset the CPU if needed */
181 if (reset_needed)
182 reset_with_rli();
183#endif
Mike Nussf66e2c82008-02-20 11:54:20 -0500184
Stefan Roesefe7cca72010-05-19 11:13:24 +0200185#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
186 u32 reg;
187
188 /*
189 * See "9.2.1.1 Booting with Option E" in the 460EX/GT
190 * users manual
191 */
192 mfcpr(CPR0_PLLC, reg);
193 if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
194 /*
195 * Set engage bit
196 */
197 reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
198 mtcpr(CPR0_PLLC, reg);
199
200 /* Now reset the CPU */
201 reset_with_rli();
Mike Nussf66e2c82008-02-20 11:54:20 -0500202 }
203#endif
204}
205
Steven A. Falco644362c2011-05-05 10:08:35 -0400206#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
207void
208chip_21_errata(void)
209{
210 /*
211 * See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that
212 * sometimes reading the PVR and/or SDR0_ECID results in incorrect
213 * values. Since the rev-D chip uses the SDR0_ECID bits to control
214 * internal features, that means the second PCIe or ethernet of an EX
215 * variant could fail to work. Also, security features of both EX and
216 * EXr might be incorrectly disabled.
217 *
218 * The suggested workaround is as follows (covering rev-C and rev-D):
219 *
220 * 1.Read the PVR and SDR0_ECID3.
221 *
222 * 2.If the PVR matches an expected Revision C PVR value AND if
223 * SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
224 * Revision C: continue executing the initialization code (no reset
225 * required). else go to step 3.
226 *
227 * 3.If the PVR matches an expected Revision D PVR value AND if
228 * SDR0_ECID3[10:11] matches its expected value, then continue
229 * executing initialization code, no reset required. else write
230 * DBCR0[RST] = 0b11 to generate a SysReset.
231 */
232
233 u32 pvr;
234 u32 pvr_28_31;
235 u32 ecid3;
236 u32 ecid3_10_11;
237 u32 ecid3_12_15;
238
239 /* Step 1: */
240 pvr = get_pvr();
241 mfsdr(SDR0_ECID3, ecid3);
242
243 /* Step 2: */
244 pvr_28_31 = pvr & 0xf;
245 ecid3_10_11 = (ecid3 >> 20) & 0x3;
246 ecid3_12_15 = (ecid3 >> 16) & 0xf;
247 if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
248 (pvr_28_31 != ecid3_12_15)) {
249 /* No reset required. */
250 return;
251 }
252
253 /* Step 3: */
254 if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
255 (ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
256 /* No reset required. */
257 return;
258 }
259
260 /* Reset required. */
261 __asm__ __volatile__ ("sync; isync");
262 mtspr(SPRN_DBCR0, 0x30000000);
263}
264#endif
265
wdenk4a9cbbe2002-08-27 09:48:53 +0000266/*
267 * Breath some life into the CPU...
268 *
Mike Nussf66e2c82008-02-20 11:54:20 -0500269 * Reconfigure PLL if necessary,
270 * set up the memory map,
wdenk4a9cbbe2002-08-27 09:48:53 +0000271 * initialize a bunch of registers
272 */
273void
274cpu_init_f (void)
275{
Stefan Roesef5564832008-08-21 11:05:03 +0200276#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
Stefan Roese745d8a02008-06-28 14:56:17 +0200277 u32 val;
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100278#endif
Stefan Roese5de85142008-06-26 17:36:39 +0200279
Steven A. Falco644362c2011-05-05 10:08:35 -0400280#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
281 chip_21_errata();
282#endif
283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284 reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100285
Tirumala Marri1b8fec12010-09-28 14:15:14 -0700286#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900287 !defined(CONFIG_SYS_4xx_GPIO_TABLE)
stroeseb867d702003-05-23 11:18:02 +0000288 /*
289 * GPIO0 setup (select GPIO or alternate function)
290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#if defined(CONFIG_SYS_GPIO0_OR)
292 out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
Stefan Roesee0a46552006-10-12 19:43:29 +0200293#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#if defined(CONFIG_SYS_GPIO0_ODR)
295 out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
Stefan Roesee0a46552006-10-12 19:43:29 +0200296#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297 out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
298 out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
299 out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
300 out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
301 out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
302 out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
303#if defined(CONFIG_SYS_GPIO0_ISR2H)
304 out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
305 out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200306#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#if defined (CONFIG_SYS_GPIO0_TCR)
308 out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200309#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
stroeseb867d702003-05-23 11:18:02 +0000311
Stefan Roesebec92642007-12-28 15:53:46 +0100312#if defined (CONFIG_405EP)
stroeseb867d702003-05-23 11:18:02 +0000313 /*
314 * Set EMAC noise filter bits
315 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200316 mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
stroeseb867d702003-05-23 11:18:02 +0000317#endif /* CONFIG_405EP */
318
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
Stefan Roese0d974d52007-03-24 15:57:09 +0100320 gpio_set_chip_configuration();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200322
wdenk4a9cbbe2002-08-27 09:48:53 +0000323 /*
324 * External Bus Controller (EBC) Setup
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
Matthias Fuchs3fb85882013-08-07 12:10:38 +0200327#if (defined(CONFIG_405GP) || \
Stefan Roesee01bd212007-03-21 13:38:59 +0100328 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200329 defined(CONFIG_405EX) || defined(CONFIG_405))
wdenk4a9cbbe2002-08-27 09:48:53 +0000330 /*
331 * Move the next instructions into icache, since these modify the flash
332 * we are running from!
333 */
334 asm volatile(" bl 0f" ::: "lr");
335 asm volatile("0: mflr 3" ::: "r3");
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200336 asm volatile(" addi 4, 0, 14" ::: "r4");
wdenk4a9cbbe2002-08-27 09:48:53 +0000337 asm volatile(" mtctr 4" ::: "ctr");
338 asm volatile("1: icbt 0, 3");
339 asm volatile(" addi 3, 3, 32" ::: "r3");
340 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
341 asm volatile(" addis 3, 0, 0x0" ::: "r3");
342 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
343 asm volatile(" mtctr 3" ::: "ctr");
344 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
Stefan Roesea4c8d132006-06-02 16:18:04 +0200345#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000346
Stefan Roesed1c3b272009-09-09 16:25:29 +0200347 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
348 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000349#endif
350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
Stefan Roesed1c3b272009-09-09 16:25:29 +0200352 mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
353 mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000354#endif
355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
Stefan Roesed1c3b272009-09-09 16:25:29 +0200357 mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
358 mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000359#endif
360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
Stefan Roesed1c3b272009-09-09 16:25:29 +0200362 mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
363 mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000364#endif
365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
Stefan Roesed1c3b272009-09-09 16:25:29 +0200367 mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
368 mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000369#endif
370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
Stefan Roesed1c3b272009-09-09 16:25:29 +0200372 mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
373 mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000374#endif
375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
Stefan Roesed1c3b272009-09-09 16:25:29 +0200377 mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
378 mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000379#endif
380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
Stefan Roesed1c3b272009-09-09 16:25:29 +0200382 mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
383 mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000384#endif
385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#if defined (CONFIG_SYS_EBC_CFG)
387 mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
Heiko Schocherca43ba12007-01-11 15:44:44 +0100388#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000389
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100390#if defined(CONFIG_WATCHDOG)
Stefan Roesef4720692010-10-04 11:09:40 +0200391 val = mfspr(SPRN_TCR);
Stefan Roese846b0dd2005-08-08 12:42:22 +0200392#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200393 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
Igor Lisitsina11e0692007-03-28 19:06:19 +0400394#elif defined(CONFIG_440EPX)
395 val |= 0xb0000000; /* generate system reset after 1.34 seconds */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200396#else
wdenk4a9cbbe2002-08-27 09:48:53 +0000397 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200398#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#if defined(CONFIG_SYS_4xx_RESET_TYPE)
Stefan Roese1c2ce222006-11-27 14:12:17 +0100400 val &= ~0x30000000; /* clear WRC bits */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401 val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100402#endif
Stefan Roesef4720692010-10-04 11:09:40 +0200403 mtspr(SPRN_TCR, val);
wdenk4a9cbbe2002-08-27 09:48:53 +0000404
Stefan Roesef4720692010-10-04 11:09:40 +0200405 val = mfspr(SPRN_TSR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000406 val |= 0x80000000; /* enable watchdog timer */
Stefan Roesef4720692010-10-04 11:09:40 +0200407 mtspr(SPRN_TSR, val);
wdenk4a9cbbe2002-08-27 09:48:53 +0000408
409 reset_4xx_watchdog();
410#endif /* CONFIG_WATCHDOG */
Stefan Roese745d8a02008-06-28 14:56:17 +0200411
Stefan Roese5de85142008-06-26 17:36:39 +0200412#if defined(CONFIG_440GX)
413 /* Take the GX out of compatibility mode
414 * Travis Sawyer, 9 Mar 2004
415 * NOTE: 440gx user manual inconsistency here
416 * Compatibility mode and Ethernet Clock select are not
417 * correct in the manual
418 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200419 mfsdr(SDR0_MFR, val);
Stefan Roese5de85142008-06-26 17:36:39 +0200420 val &= ~0x10000000;
Stefan Roesed1c3b272009-09-09 16:25:29 +0200421 mtsdr(SDR0_MFR,val);
Stefan Roese5de85142008-06-26 17:36:39 +0200422#endif /* CONFIG_440GX */
423
Stefan Roese745d8a02008-06-28 14:56:17 +0200424#if defined(CONFIG_460EX)
425 /*
426 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
427 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
428 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
429 */
430 mfsdr(SDR0_AHB_CFG, val);
431 val |= 0x80;
432 val &= ~0x40;
433 mtsdr(SDR0_AHB_CFG, val);
434 mfsdr(SDR0_USB2HOST_CFG, val);
435 val &= ~0xf00;
436 val |= 0x400;
437 mtsdr(SDR0_USB2HOST_CFG, val);
438#endif /* CONFIG_460EX */
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700439
Stefan Roesef5564832008-08-21 11:05:03 +0200440#if defined(CONFIG_405EX) || \
441 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700442 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Masahiro Yamada9ed32462014-09-29 01:37:59 +0900443 defined(CONFIG_460SX)
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700444 /*
445 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
446 */
Stefan Roese5e7abce2010-09-11 09:31:43 +0200447 mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
448 PLB4Ax_ACR_RDP_4DEEP);
449 mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
450 PLB4Ax_ACR_RDP_4DEEP);
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700451#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
wdenk4a9cbbe2002-08-27 09:48:53 +0000452}
453
454/*
455 * initialize higher level parts of CPU like time base and timers
456 */
457int cpu_init_r (void)
458{
stroeseb867d702003-05-23 11:18:02 +0000459#if defined(CONFIG_405GP)
stroese38daa272003-03-20 15:21:50 +0000460 uint pvr = get_pvr();
wdenk4a9cbbe2002-08-27 09:48:53 +0000461
462 /*
stroese38daa272003-03-20 15:21:50 +0000463 * Set edge conditioning circuitry on PPC405GPr
464 * for compatibility to existing PPC405GP designs.
465 */
stroesebaa3d522003-04-04 16:00:33 +0000466 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
Stefan Roesed1c3b272009-09-09 16:25:29 +0200467 mtdcr(CPC0_ECR, 0x60606000);
stroese38daa272003-03-20 15:21:50 +0000468 }
stroeseb867d702003-05-23 11:18:02 +0000469#endif /* defined(CONFIG_405GP) */
Stefan Roese2801b2d2008-03-11 15:05:50 +0100470
Stefan Roese9cd69012009-02-23 16:42:51 +0100471 return 0;
wdenk4a9cbbe2002-08-27 09:48:53 +0000472}
Stefan Roese5e47f952009-10-19 14:06:23 +0200473
474#if defined(CONFIG_PCI) && \
475 (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
476 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
477/*
478 * 440EP(x)/GR(x) PCI async/sync clocking restriction:
479 *
480 * In asynchronous PCI mode, the synchronous PCI clock must meet
481 * certain requirements. The following equation describes the
482 * relationship that must be maintained between the asynchronous PCI
483 * clock and synchronous PCI clock. Select an appropriate PCI:PLB
484 * ratio to maintain the relationship:
485 *
486 * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
487 */
488static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
489{
490 if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
491 return 0;
492 else
493 return 1;
494}
495
496int ppc4xx_pci_sync_clock_config(u32 async)
497{
498 sys_info_t sys_info;
499 u32 sync;
500 int div;
501 u32 reg;
502 u32 spcid_val[] = {
503 CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
504 CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
505
506 get_sys_info(&sys_info);
507 sync = sys_info.freqPCI;
508
509 /*
510 * First check if the equation above is met
511 */
512 if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
513 /*
514 * Reconfigure PCI sync clock to meet the equation.
515 * Start with highest possible PCI sync frequency
516 * (divider 1).
517 */
518 for (div = 1; div <= 4; div++) {
519 sync = sys_info.freqPLB / div;
520 if (ppc4xx_pci_sync_clock_ok(sync, async))
521 break;
522 }
523
524 if (div <= 4) {
525 mtcpr(CPR0_SPCID, spcid_val[div]);
526
527 mfcpr(CPR0_ICFG, reg);
528 reg |= CPR0_ICFG_RLI_MASK;
529 mtcpr(CPR0_ICFG, reg);
530
531 /* do chip reset */
532 mtspr(SPRN_DBCR0, 0x20000000);
533 } else {
534 /* Impossible to configure the PCI sync clock */
535 return -1;
536 }
537 }
538
539 return 0;
540}
541#endif